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AFS090 数据表(PDF) 163 Page - Microsemi Corporation |
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AFS090 数据表(HTML) 163 Page - Microsemi Corporation |
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163 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 147 Temporary overshoots are allowed according to Table 3-4 on page 3-4. Solution 2 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and Zener, as shown in Figure 2- 102. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Figure 2-101 • Solution 1 Figure 2-102 • Solution 2 On-Chip Off-Chip Solution 1 5.5 V 3.3 V Requires two board resistors, LVCMOS 3.3 V I/Os Fusion I/O Input Rext1 Rext2 Solution 2 5.5 V 3.3 V Requires one board resistor, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os Fusion I/O Input Rext1 Zener 3.3 V On-Chip Off-Chip |
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