 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AFS090 数据表(PDF) 167 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
AFS090 数据表(HTML) 167 Page - Microsemi Corporation |
|
|
167 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 151 Selectable Skew between Output Buffer Enable/Disable Time The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time. Figure 2-105 • Block Diagram of Output Enable Path Figure 2-106 • Timing Diagram (option1: bypasses skew circuit) Figure 2-107 • Timing Diagram (option 2: enables skew circuit) ENABLE (OUT) Skew Circuit Output Enable (from FPGA core) I/O Output Buffers ENABLE (IN) MUX Skew Select ENABLE (IN) ENABLE (OUT) Less than 0.1 ns Less than 0.1 ns ENABLE (IN) ENABLE (OUT) 1.2 ns (typical) Less than 0.1 ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
