WM8321 datasheet(37/253 Pages) WOLFSON

37 / 253 page

Production Data

WM8321

PD, February 2012, Rev 4.0

11.6 ON PIN FUNCTION

The ON

¯¯ pin is intended for connection to the master power switch on the user’s application. It can be

used to start-up the WM8321 from the SLEEP or OFF states and also to power down the system.

This pin operates on the LDO12 (VPMIC) power domain and has an internal pull-up resistor. This pin

is asserted by shorting it to GND. A de-bounce circuit is provided on this input pin.

The behaviour of the ON

¯¯ pin is programmable. The primary action taken on asserting this pin is

determined by the ON_PIN_PRIMACT register field. Note that the ON_PIN_INT interrupt event is

always raised when the ON

¯¯ pin is asserted.

If the pin is held asserted for longer than the timeout period set by ON_PIN_TO, then a secondary

action is executed. The secondary action is determined by the ON_PIN_SECACT register field.

If the pin is held asserted for a further timeout period, then a tertiary action is executed. The tertiary

action is not programmable, and is to generate an OFF request.

The status of the ON

¯¯ pin can be read at any time via the ON_PIN_STS register.

Note that the ON

¯¯ pin control registers are locked by the WM8321 User Key. These registers can only

be changed by writing the appropriate code to the Security register, as described in Section 12.4.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16389

(4005h) ON

Pin Control

9:8

ON_PIN_SECACT

Secondary action of ON

¯¯ pin (taken

after 1 timeout period)

00 = Interrupt

01 = ON request

10 = OFF request

11 = Reserved

Protected by user key

5:4

ON_PIN_PRIMACT

Primary action of ON

¯¯ pin

00 = Ignore

01 = ON request

10 = OFF request

11 = Reserved

Note that an Interrupt is always

raised.

Protected by user key

ON_PIN_STS

Current status of ON

¯¯ pin

0 = Asserted (logic 0)

1 = Not asserted (logic 1)

1:0

ON_PIN_TO

¯¯ pin timeout period

00 = 1s

01 = 2s

10 = 4s

11 = 8s

Protected by user key

Table 5 ON Pin Control Registers

The ON

¯¯ pin interrupt event is always raised as part of the primary action when the ON

¯¯ pin is asserted

or de-asserted. (Note that the ON

¯¯ pin interrupt is raised on the rising and falling edges of this ON

¯¯ pin

input signal.) The ON

¯¯ pin interrupt is a selectable option as the secondary action.

The ON

¯¯ pin interrupt event is indicated by the ON_PIN_CINT register field. This secondary interrupt

triggers a primary ON Pin Interrupt, ON_PIN_INT (see Section 23). This can be masked by setting the

mask bit as described in Table 6.

WM8321 数据表(PDF) 37 Page - Wolfson Microelectronics plc

WM8321 数据表(HTML) 37 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

WM8321 数据表(PDF) 37 Page - Wolfson Microelectronics plc

WM8321 数据表(HTML) 37 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载