WM8321 datasheet(63/253 Pages) WOLFSON

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Production Data

WM8321

PD, February 2012, Rev 4.0

15.3 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL

The DC-DC Converters (1-4) and LDO Regulators (1-11) may be programmed to switch on in a

selected timeslot within the ON sequence using the DCm_ON_SLOT or LDOn_ON_SLOT fields.

These register fields are defined in Section 15.11.2 and Section 15.11.3. Alternatively, these fields

can be used to assign a converter / regulator to one of the Hardware Enable Inputs. (The Hardware

Enable Inputs are alternate functions supported via GPIO - see Section 21.)

Converters / regulators which are assigned to one of the Hardware Enable Inputs are enabled or

disabled according to the logic level of the respective GPIO input in the ON or SLEEP power states.

The Hardware Enable Inputs are effective from the end of the ON sequence until the start of the OFF

sequence. Note that the GPIO Hardware Enable function is not the same as the GPIO Hardware

Control function.

Any converters / regulators which are assigned to timeslots within the ON sequence will be disabled

in the reverse sequence when an OFF sequence is scheduled. Any converters / regulators which are

not assigned to timeslots, or are assigned to Hardware Enable Inputs, will be disabled immediately at

the start of the OFF sequence.

Each of the converters / regulators may also be programmed to be disabled in a selected timeslot

within the SLEEP sequence using the DCm_SLP_SLOT or LDOn_SLP_SLOT fields. In the case of

converters / regulators which are not disabled by the SLEEP sequence, these fields determine in

which timeslot each converter or regulator enters its SLEEP configuration.

Any converters / regulators which are disabled as part of the SLEEP sequence will be enabled in the

reverse sequence when a WAKE transition is scheduled.

By default, the OFF sequence is the reverse of the ON sequence. Similarly, the WAKE sequence is

the reverse of the SLEEP sequence. If a different behaviour is required, this can be achieved by

writing to the _ON_SLOT or _SLP_SLOT registers between transitions in order to re-define the

sequences.

Any converters / regulators which are assigned to Hardware Enable Inputs will remain under control

of the Hardware Enable Inputs in the SLEEP power state. In this case, the DCm_SLP_SLOT or

LDOn_SLP_SLOT fields determine in which timeslot the converter / regulator enters its SLEEP

configuration.

The WM8321 will control the DCm_ENA or LDOn_ENA bit (see Section 15.2) for any converter /

regulator that is enabled or disabled during the power state transitions. In the case of a converter /

regulator assigned to a Hardware Enable (GPIO) input, the DCm_ENA or LDOn_ENA bit is not

controlled and the converter / regulator is not affected by this bit.

The DC-DC converters include a soft-start feature that limits in-rush current at start-up. However, in

order to further reduce supply in-rush current, it is recommended that the individual converters are

programmed to start up in different time slots within the start-up sequence, as described in

Section 11.3.

Similarly, it is recommended that the individual LDO regulators are programmed to start up in different

time slots within the start-up sequence, as described in Section 11.3.

The External Power Enable (EPE) outputs, EPE1 and EPE2, may also be assigned to timeslots in the

ON / SLEEP sequences or assigned to Hardware Enable inputs using the EPEn_ON_SLOT and

EPEn_SLP_SLOT fields described in 15.11.4.

Note that a transition from the SLEEP state to the OFF state is not a controlled transition. If an ‘OFF’

event occurs whilst in the SLEEP state, then the WM8321 will select the OFF state, but all the

enabled converters and regulators will be disabled immediately; the time-controlled sequence is not

implemented in this case. See Section 11.3 for details of the WM8321 ‘OFF’ events.

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