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WM8321 数据表(PDF) 59 Page - Wolfson Microelectronics plc |
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WM8321 数据表(HTML) 59 Page - Wolfson Microelectronics plc |
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59 / 253 page  Production Data WM8321 w PD, February 2012, Rev 4.0 59 The remaining contents of DCRW Page 2 include the registers listed in Table 27, which are defined in other sections of this datasheet. REGISTER FUNCTION REFERENCE DC1_ON_SLOT [2:0] DC-DC Converter 1 See Section 15.11.2 DC1_FREQ [1:0] See Section 15.11.2 DC1_PHASE See Section 15.11.2 DC1_ON_VSEL [6:2] See Section 15.11.2 DC1_CAP [1:0] See Section 15.11.2 DC2_ON_SLOT [2:0] DC-DC Converter 2 See Section 15.11.2 DC2_FREQ [1:0] See Section 15.11.2 DC2_PHASE See Section 15.11.2 DC2_ON_VSEL [6:2] See Section 15.11.2 DC2_CAP [1:0] See Section 15.11.2 DC3_ON_SLOT [2:0] DC-DC Converter 3 See Section 15.11.2 DC3_PHASE [1:0] See Section 15.11.2 DC3_ON_VSEL [6:2] See Section 15.11.2 DC3_CAP [1:0] See Section 15.11.2 DC4_ON_SLOT [2:0] DC-DC Converter 4 See Section 15.11.2 DC4_PHASE [1:0] See Section 15.11.2 DC4_ON_VSEL [6:2] See Section 15.11.2 DC4_CAP [1:0] See Section 15.11.2 LDO1_ON_SLOT [2:0] LDO Regulator 1 See Section 15.11.3 LDO1_ON_VSEL [4:0] See Section 15.11.3 LDO2_ON_SLOT [2:0] LDO Regulator 2 See Section 15.11.3 LDO2_ON_VSEL [4:0] See Section 15.11.3 LDO3_ON_SLOT [2:0] LDO Regulator 3 See Section 15.11.3 LDO3_ON_VSEL [4:0] See Section 15.11.3 LDO4_ON_SLOT [2:0] LDO Regulator 4 See Section 15.11.3 LDO4_ON_VSEL [4:0] See Section 15.11.3 LDO5_ON_SLOT [2:0] LDO Regulator 5 See Section 15.11.3 LDO5_ON_VSEL [4:0] See Section 15.11.3 LDO6_ON_SLOT [2:0] LDO Regulator 6 See Section 15.11.3 LDO6_ON_VSEL [4:0] See Section 15.11.3 LDO7_ON_SLOT [2:0] LDO Regulator 7 See Section 15.11.3 LDO7_ON_VSEL [4:0] See Section 15.11.3 LDO8_ON_SLOT [2:0] LDO Regulator 8 See Section 15.11.3 LDO8_ON_VSEL [4:0] See Section 15.11.3 Table 27 DCRW Page 2 14.6.4 DCRW PAGE 3 Page 3 of the DCRW occupies register addresses R30744 (7818h) to R30751 (781Fh). This contains user-programmable data. This page of data is normally loaded from OTP when ‘ON’ state transition is scheduled (except in Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command. This page of data is loaded from the second page of ICE memory (10h to 1Fh) when ‘ON’ state transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be loaded from ICE using the ICE Read command. Note that ICE Address 10h corresponds to bits 15:8 at the start address of DCRW Page 3; ICE Address 11h corresponds to bits 7:0 at the same DCRW address. The contents of DCRW Page 3 include the registers listed in Table 28. |
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