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WM8321 数据表(PDF) 38 Page - Wolfson Microelectronics plc |
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WM8321 数据表(HTML) 38 Page - Wolfson Microelectronics plc |
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38 / 253 page  WM8321 Production Data w PD, February 2012, Rev 4.0 38 ADDRESS BIT LABEL DESCRIPTION R16401 (4011h) Interrupt Status 1 12 ON_PIN_CINT ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. R16409 (4019h) Interrupt Status 1 Mask 12 IM_ON_PIN_CINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 6 ON Pin Interrupt 11.7 RESET PIN FUNCTION The RESET ¯¯¯¯¯¯ pin is an active low input/output which is used to command Hardware Resets in the WM8321 and in other connected devices. The pin is an open-drain type, with integrated pull-up; it can be driven low by external sources or by the WM8321 itself. The WM8321 drives the RESET ¯¯¯¯¯¯ pin low in the OFF state. The output status of the RESET ¯¯¯¯¯¯ pin in SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7. The WM8321 clears the RESET ¯¯¯¯¯¯ pin following the transition to ON. On completion of the state transition, the RESET ¯¯¯¯¯¯ pin is held low for a further delay time period, extending the RESET ¯¯¯¯¯¯ low duration. The RESET ¯¯¯¯¯¯ delay period is set by the RST_DUR register bit. See Figure 6 for further details. The WM8321 detects a Hardware Reset request whenever the RESET ¯¯¯¯¯¯ pin is driven low by an external source. In this event, the WM8321 resets the internal control registers (excluding the RTC) and initiates a start-up sequence. See Section 24. It is possible to mask the RESET ¯¯¯¯¯¯ pin input in the SLEEP state by setting the RST_SLP_MSK register bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8321 will take no action if the RESET ¯¯¯¯¯¯ pin is pulled low. Note that the RESET ¯¯¯¯¯¯ pin control registers are locked by the WM8321 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS BIT LABEL DEFAULT DESCRIPTION R16390 (4006h) Reset Control 5 RST_SLP_MSK 1 Masks the RESET ¯¯¯¯¯¯ pin input in SLEEP mode 0 = External RESET ¯¯¯¯¯¯ active in SLEEP 1 = External RESET ¯¯¯¯¯¯ masked in SLEEP Protected by user key 4 RST_SLPENA 1 Sets the output status of RESET ¯¯¯¯¯¯ pin in SLEEP 0 = RESET ¯¯¯¯¯¯ high (not asserted) 1 = RESET ¯¯¯¯¯¯ low (asserted) Protected by user key 1:0 RST_DUR 11 Delay period for releasing RESET ¯¯¯¯¯¯ after ON or WAKE sequence 00 = 3ms 01 = 11ms 10 = 51ms 11 = 101ms Protected by user key Table 7 RESET Pin Control Registers |
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