WM8321 datasheet(96/253 Pages) WOLFSON

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WM8321

Production Data

PD, February 2012, Rev 4.0

17 POWER SUPPLY CONTROL

17.1 GENERAL DESCRIPTION

The primary power supply to the WM8321 is provided via the PVDD pin. This supply is required for

normal device functionality. The PVDD voltage is monitored internally to detect a low voltage

condition where the device can no longer operate. A Power Path Management Interrupt is raised

when PVDD falls below an undervoltage threshold, as described in Section 17.2.

A backup power source may be provided for the WM8321. This enables the Real Time Clock (RTC)

and other selected registers to be maintained when PVDD is not available. This is described in

Section 17.3.

17.2 POWER PATH MANAGEMENT INTERRUPTS

The Power Path Management circuit is associated with an Interrupt event flag.

The PPM_SYSLO_EINT interrupt bit is set when the internal signal SYSLO is asserted. This indicates

a PVDD undervoltage condition, described in Section 24.4. This secondary interrupt triggers a

primary Power Path Management Interrupt, PPM_INT (see Section 23). This can be masked by

setting the mask bit as described in Table 44.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

PPM_SYSLO_EINT

Power Path SYSLO interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_PPM_SYSLO_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 44 Power Path Management Interrupt

17.3 BACKUP POWER

As an option, a backup power source can be provided for the WM8321. This is provided using a coin

cell, super/gold capacitor, or else a standard capacitor, connected to the LDO12VOUT pin.

Note that a 22kΩ series resistor should also be connected to the backup power source.

The LDO12VOUT pin provides a constant voltage output for charging the backup power source

whenever the PVDD power domain is available.

The purpose of the backup is to power the always-on functions such as the crystal oscillator, RTC and

ALARM control registers. The backup power also maintains a ‘software scratch’ memory area in the

even when the main battery is removed and no other power supply is available.

The backup duration will vary depending upon the backup power source characteristics. A typical coin

cell can provide power to the WM8321 in BACKUP mode for a month or more whilst also maintaining

the RTC and the ‘software scratch’ register.

If a standard capacitor is used as the backup power source, then it is particularly important to

minimise the device power consumption in the BACKUP state. A 22

F capacitor will maintain the

device settings for up to 5 minutes in ‘unclocked’ mode, where power consumption is minimised by

stopping the RTC in the BACKUP state. The RTC is unclocked in the BACKUP state if the

XTAL_BKUPENA register field is set to 0, as described in Section 20.5.

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