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WM8321 数据表(PDF) 41 Page - Wolfson Microelectronics plc |
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WM8321 数据表(HTML) 41 Page - Wolfson Microelectronics plc |
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41 / 253 page  Production Data WM8321 w PD, February 2012, Rev 4.0 41 The sequence of signals associated with a single register write operation is illustrated in Figure 7. Figure 7 Control Interface 2-wire (I2C) Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 8. Figure 8 Control Interface 2-wire (I2C) Register Read The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 11. Note that, for multiple write and multiple read operations, the auto-increment option must be enabled. This feature is enabled by default; it is described in Table 12 below. TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge (SDA Low) A ¯¯ Not Acknowledge (SDA High) P Stop Condition R/W ¯¯ ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to WM8321 [Grey field] Data flow from WM8321 to bus master Table 11 Control Interface Terminology Figure 9 Single Register Write to Specified Address |
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