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WM8321 数据表(PDF) 66 Page - Wolfson Microelectronics plc |
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WM8321 数据表(HTML) 66 Page - Wolfson Microelectronics plc |
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66 / 253 page ![]() WM8321 Production Data w PD, February 2012, Rev 4.0 66 To ensure stable operation, the register fields DCm_CAP must be set for each of the DC-DC Converters according to the output capacitance. (Note that these fields are set via OTP/ICE settings only; they cannot be changed by writing to the control register.) The choice of output capacitor is described in Section 30.3. When a DC-DC Converter is disabled, the output pin can be configured to be floating or to be actively discharged. This is selected using DCm_FLT. DC-DC Converters 1 and 2 also support selectable switching frequency. This can either be 2MHz or 4MHz, according to the DCm_FREQ register field. (Note that these fields are set via OTP/ICE settings only; they cannot be changed by writing to the control register.) The switching frequency of DC-DC3 is fixed at 2MHz. Note that the supported output voltage range for DC-DC Converters 1 and 2 is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The switching phase of each DC-DC converter can be set using the DCm_PHASE bits. Where two converters are operating at the same switching frequency, the supply current ripple can be minimised by selecting a different switching phase for each converter. The Dynamic Voltage Scaling (DVS) feature on DC-DC1 and DC-DC2 enables hardware or software selection of an alternate output voltage, DCm_DVS_VSEL. This may be useful if a short-term variation in output voltage is required. The DVS voltage (set by DCm_DVS_VSEL) may be selected by setting DCm_DVS_SRC = 01. Alternatively, the DVS voltage may be selected under control of one of the Hardware DVS Control inputs supported via the GPIO pins. See Section 21 for details of configuring the GPIO pins as Hardware DVS Control inputs. Whenever the DVS voltage is selected by any method, the DVS selection takes precedence over the ON, SLEEP or Hardware Control (HWC) configuration. See Section 15.8 for details of Hardware Control options. The output voltage ramp rate is selectable for DC-DC Converters 1 and 2. The DCm_RATE field selects the rate of change of output voltage, whether this is in response to an operating mode transition, or any hardware or software command. Note that the DCm_RATE field is accurate in Forced Continuous Conduction Mode (FCCM); in other modes, the actual slew rate may be longer in the case of a decreasing output voltage selection, especially under light load conditions. The WM8321 can indicate the status of the Dynamic Voltage Scaling via a GPIO pin configured as a “DC-DC1 DVS Done” or “DC-DC2 DVS Done” output (see Section 21). When a GPIO pin is configured to indicate the DVS status, this signal is temporarily de-asserted during a DVS transition on the associated DC-DC Converter, and is subsequently asserted to indicate the transition has completed. Note that the GPIO DVS outputs indicate the progress of all output voltage slews; they are not limited to transitions associated with DCm_DVS_SRC; the GPIO DVS output also indicates the status of a slew caused by a write to the DCm_ON_VSEL register, or a slew to the DCm_SLP_VSEL voltage. Note also that the GPIO DVS outputs are indicators of the DVS control mechanism only; they do not confirm the output voltage accuracy. The output voltage can be checked using the voltage status bits if required (see Section 15.2). 15.6.1 DC-DC3 / DC-DC4 DUAL MODE DC-DC Converters 3 and 4 can be configured to operate in ‘Dual’ mode, where the two converters are ganged together to support an increased current capability. In this mode, the two converters employ a common voltage feedback circuit in order to ensure the two outputs are accurately aligned.The dual mode is selected by configuring DC-DC4 as a ‘Slave’ to DC-DC3. When the DC4_SLV register is set, then DC-DC4 comes under the control of the DC-DC3 registers, and both converters are controlled together. All other DC-DC4 control registers have no effect when DC4_SLV is set. Note that the DC4_SLV register can only be controlled via OTP/ICE configuration; it cannot be changed by writing to the control register. |
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