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WM8321 数据表(PDF) 28 Page - Wolfson Microelectronics plc |
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WM8321 数据表(HTML) 28 Page - Wolfson Microelectronics plc |
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28 / 253 page  WM8321 Production Data w PD, February 2012, Rev 4.0 28 Figure 2 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) Figure 3 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions TJ = -40ºC to +125 ºC unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT CS ¯¯ falling edge to SCLK1 rising edge tCSU 40 ns SCLK1 falling edge to CS ¯¯ rising edge tCHO 10 ns SCLK1 pulse cycle time tSCY 200 ns SCLK1 pulse width low tSCL 80 ns SCLK1 pulse width high tSCH 80 ns SDA1 to SCLK1 set-up time tDSU 40 ns SDA1 to SCLK1 hold time tDHO 10 ns Pulse width of spikes that will be suppressed tps 0 5 ns SCLK1 falling edge to SDOUT1 transition tDL 40 ns The CS ¯¯ pin must be held high for at least 1 s after every register write operation in SPI mode. |
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