WM8321 datasheet(119/253 Pages) WOLFSON

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Production Data

WM8321

PD, February 2012, Rev 4.0

119

23 INTERRUPT CONTROLLER

The WM8321 has a comprehensive Interrupt logic capability. The dedicated IRQ

¯¯¯ pin can be used to

alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be

individually enabled or masked. Following an interrupt event, the host processor should read the

interrupt registers in order to determine what caused the interrupt, and take appropriate action if

required.

The WM8321 interrupt controller has two levels:

Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by

setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger

condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register

bit. Note that reading the register does not clear the secondary interrupt.

Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts

associated with one particular circuit block). Each of the secondary interrupts can be individually

masked or enabled as an input to the corresponding primary interrupt. The primary interrupt register

R16400 (4010h) is read-only.

The status of the IRQ

¯¯¯ pin reflects the logical NOR of the primary interrupts. A logic 0 indicates that

one or more of the primary interrupts is asserted. Each of the primary interrupts can be individually

masked or enabled as an input to the IRQ

¯¯¯ pin output.

The IRQ

¯¯¯ pin output can either be CMOS driven or Open Drain (integrated pull-up) configuration, as

determined by the IRQ_OD register bit. When the IRQ

¯¯¯ pin is Open Drain, it is actively driven low when

asserted; the pull-up causes a logic high output when not asserted. The Open Drain configuration

enables multiple devices to share a common Interrupt line with the host processor.

The IRQ

¯¯¯ pin output can be masked by setting the IM_IRQ register bit. When the IRQ

¯¯¯ pin is masked, it

is held in the logic 1 (or Open Drain) state regardless of any internal interrupt event.

Note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether

the bit is enabled or masked as an input to the corresponding primary interrupt. The primary interrupt

bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of

whether the primary interrupt bit is enabled or masked as an input to the IRQ

¯¯¯ pin output.

Note also that if any internal condition is configured to trigger an event other than an Interrupt (eg. the

Watchdog timer triggers Reset), these events are always actioned, regardless of the state of any

interrupt mask bits.

The IRQ

¯¯¯ pin output is configured using the register bits described in Table 63.

ADDRESS

BIT

LABEL

DESCRIPTION

R16407

(4017h)

IRQ Config

IRQ_OD

IRQ pin configuration

0 = CMOS

1 = Open Drain (integrated pull-up)

IM_IRQ

IRQ pin output mask

0 = Normal

1 = IRQ output is masked

Table 63 IRQ Pin Configuration

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