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WM8321 数据表(PDF) 145 Page - Wolfson Microelectronics plc

部件名 WM8321
功能描述  Processor Power Management Subsystem
PDF  253 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8321 数据表(HTML) 145 Page - Wolfson Microelectronics plc

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Production Data
WM8321
w
PD, February 2012, Rev 4.0
145
29 REGISTER BITS BY ADDRESS
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R0 (00h)
Reset ID
15:0
CHIP_ID [15:0] 0000_0000
_0000_000
0
Writing to this register causes a Software Reset. The
register map contents may be reset, depending on
SW_RESET_CFG.
Reading from this register will indicate Chip ID.
Register 00h
Reset ID
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R1 (01h)
Revision
15:8
PARENT_REV
[7:0]
0000_0000 The revision number of the parent die
7:0
CHILD_REV
[7:0]
0000_0000 The revision number of the child die (when present)
Register 01h
Revision
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R16384
(4000h)
Parent ID
15:0
PARENT_ID
[15:0]
0110_0010
_0100_011
0
The ID of the parent die
Register 4000h
Parent ID
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R16385
(4001h)
PVDD
Control
15:14
SYSLO_ERR_
ACT [1:0]
00
SYSLO Error Action
Selects the action taken when SYSLO is asserted
00 = Interrupt
01 = WAKE transition
10 = Reserved
11 = OFF transition
11
SYSLO_STS
0
SYSLO Status
0 = Normal
1 = PVDD is below SYSLO threshold
6:4
SYSLO_THR
[2:0]
010
SYSLO threshold (falling PVDD)
This is the falling PVDD voltage at which SYSLO will be
asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
2:0
SYSOK_THR
[2:0]
101
SYSOK threshold (rising PVDD)
This is the rising PVDD voltage at which SYSOK will be
asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is added to
these threshold levels.
Register 4001h
PVDD Control



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