CS1630-FSZ datasheet(16/56 Pages) APEX

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CS1630/31

DS954F2

"Configuration 54 (Config54) – Address 86" on page 46) is set

to ‘1’, and the system returns to normal operation. If bit

BOP_RSTART is set to ‘0’, a boost overvoltage fault is latched

and the system stays in the fault mode until the input power is

recycled.

5.7 Voltage Clamp Circuit

To keep dimmers conducting and prevent them from misfiring,

a minimum power needs to be delivered from the dimmer to

the load. This power is nominally around 2W for 230V and

120V TRIAC dimmers. At low dim angles (

90°), this excess

power cannot be converted into light by the second stage due

to the dim mapping at light loads. The output voltage of the

boost stage (VBST) can rise above the safe operating voltage

of the primary-side bulk capacitor C8.

The CS1630/31 provides active clamp circuitry on the CLAMP

pin, as shown in Figure 14.

Figure 14. CLAMP Pin Model

A PWM control loop ensures that the voltage on VBST does not

exceed 227V for 120VAC applications or 424V for 230VAC

applications. This control turns on the BJT of the voltage

clamp circuit, allowing the clamp circuit to sink current through

the load resistor, preventing VBST from exceeding the

maximum safe voltage.

5.7.1 Clamp Overpower Protection

The CS1630/31 clamp overpower protection (COP) control

logic continuously monitors the ‘ON’ time of the clamp circuit.

If the cumulative 'ON' time exceeds 84.48ms during the

internally generated 1 second window time, a COP event is

actuated, disabling the boost and second stages. The clamp

circuitry is turned off during the fault event.

5.8 Quasi-resonant Second Stage

The second stage is a quasi-resonant current-regulated DC-

DC converter capable of flyback, buck, or tapped buck

operation. The second stage output configuration is set by bit

S2CONFIG in register Config12 (see "Configuration 12

(Config12) – Address 44" on page 36) and bits BUCK[3:0] in

42" on page 35). To deliver the highest possible efficiency, the

second stage can operate in quasi-resonant mode and

provides constant output current with minimum line-frequency

ripple. Primary-side control is used to simplify system design

and reduce system cost and complexity.

The digital algorithm ensures monotonic dimming from 0% to

100% of the dimming range with a linear relationship between

the dimming signal and the LED current. Figure 15 illustrates

a quasi-resonant flyback stage configured for two-channel

parallel output.

Figure 15. Flyback Parallel Output Model

The flyback stage is controlled by measuring current in the

transformer primary and voltage on the auxiliary winding.

Quasi-resonant

operation

achieved

detecting

transformer flyback using an auxiliary winding.

A quasi-resonant buck stage configured for two-channel

parallel output is illustrated in Figure 16.

Figure 16. Buck Parallel Output Model

CLAMP

R10

ICLAMP

VBST

CS1630 /31

VBE

VDD

R13

R11

R14

CS1630 /31

FBAUX

GND

FBSENSE

BS T

R12

C11

C12

D11

R15 D10

R16

C10

IGND

LED2+

LED 1+

LED 1-

LED2-

GND

VCC

R13

R11

R14

CS1630 /31

FBAUX

GND

FBSENSE

VBST

R12

C11

C12

D11

R15 D10

R16

C10

IGND

LED 2+

LED1+

LED 1-

LED 2-

GND

VCC

CS1630-FSZ 数据表(PDF) 16 Page - Cirrus Logic

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