CS1630-FSZ datasheet(24/56 Pages) APEX

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CS1630/31

DS954F2

whether data transfer is a read or write operation. This bit

should be set to '0' to perform a write operation and '1' to

perform a read operation. The 7-bit device address is the 7

most significant bit of the slave address. For data transfers,

the CS1630/31 acknowledges a binary device address of

‘0010000’, which is reserved for accessing OTP shadow

registers (see "One-Time Programmable (OTP) Registers" on

page 27).

After the 7-bit device address is received, the Control Port

performs a compare to determine if it matches the CS1630/31

device address. If the compare is true, the Control Port will

respond with an Acknowledge (bit A) and prepares the device

for a read or write operation. Since the CS1630/31 is always

in slave mode, the device sends an Acknowledge at the end

of each byte. The final bit is the Stop condition (bit P), which is

sent by the master to finish a data transfer.

The communication port supports single and block data

transfers. The block read or write capability is available by

setting the MSB of the register address to ‘1’. Device address

0x10 provides access to the OTP shadow registers in the

address range of 0x00 to 0x7F.

5.11.2 Control Port Enable

Control Port mode is enabled and initiated by transmitting a

two-byte hardware pass code using an I2C block write.

To enable the control port, the master needs to write a Start

condition followed by a slave address of 0x22 (7 MSB device

address = ‘0010001’ and the LSB R/W = ‘0’ for a write

operation). Then a 0x81 (MSB BLK/SGL = ‘1’ and 7 LSB

0xF4 and 0x4F, ending the transmission with a Stop condition.

Once in Control Port mode, the CS1630/31 can be configured

to perform color calibration functions and program the OTP

memory. Several other system configuration tasks can be

performed by writing and reading the shadow registers using

the I2C port.

5.11.3 Read Operation

To perform a read operation, the master must write the 7-bit

device address, the R/W bit, the Block/Single (BLK/SGL) bit,

and the 7-bit shadow register address. The master can then

read the required bytes from the shadow registers. Figure 28

illustrates protocol for a single and block read operation.

To perform a single shadow register read, a write to the

Control Port must be used to set up the shadow register

address and the BLK/SGL configuration bit (indicating a single

read operation). To initiate a single read operation, a Start

condition followed by a slave address of 0x21 (7 MSB device

address = ‘0010000’ and the LSB R/W = ‘1’ for a read

operation) is sent at the start of the message. The MSB of the

second byte is cleared to ‘0’ to indicate a single byte read. The

remaining 7 bits of the second byte represent the shadow

Acknowledge from the Control Port, the master should

terminate the message by sending a Stop condition. The

protocol for a single read operation is illustrated by the top

frame in Figure 28.

To initiate a block read operation, a Start condition followed by

a slave address of 0x21 (7 MSB device address = ‘0010000’

and the LSB R/W = ‘1’ for a read operation) is sent at the start

of the message. The MSB of the second byte is set to ‘1’ to

indicate a block read. The remaining 7 bits of the second byte

represent the starting shadow register address of the read

operation. The slave continues to send data bytes until the

master sends a Stop condition after receiving the

Acknowledge, signifying the end of the block read message.

The protocol for a block read operation is illustrated by the

bottom frame in Figure 28.

5.11.4 Write Operation

To perform a write operation, the master must write the 7-bit

device address, the R/W bit, the BLK/SGL bit, and the 7-bit

shadow register address. The master can then write the

required bytes to the shadow registers. Figure 29 illustrates

protocol for a single and block write operation.

Figure 28. Frame Formats for Read Operation

Device Address

(7-bit)

‘0’ = Single

‘1’ = Read

Start

Condition

Stop

Condition

Data Transferred

(2 Bytes and Acknowledge)

Slave Address

(1 Byte and Acknowledge)

Data

‘A’ = Acknowledge

(SDA Low)

‘1’ = Block

Device Address

(7-Bit)

Data

… ...

From Slave to Master

From Master to Slave

‘1’ = Read

Start

Condition

Stop

Condition

‘A’ = Acknowledge (SDA Low)

Data Transferred

(n Bytes and Acknowledge)

Slave Address

(1 Byte and Acknowledge)

Data

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