CS1630-FSZ datasheet(26/56 Pages) APEX

26 / 56 page

CS1630/31

DS954F2

5.12.1 Programming the OTP Memory

When the CS1630/31 is shipped, some of the OTP memory

will already be programmed. Do not clear any bits to ‘0’ that

are programmed to '1', and do not modify any registers or bits

that are reserved. Changing bits from '1' to '0' before

attempting programming is likely to result in an unrecoverable

CRC error, and changes to reserved bits may have

detrimental effects on behavior.

Step 1

Write Register and Bit Values

Write the desired values to the OTP shadow register address

locations. All reads and writes are performed with I2C

communication using device address 0x10.

Step 2

Enable Programming

Set the CRC bit to ‘1’ in register Config38 (see "Configuration

38 (Config38) – Address 70" on page 39). Setting CRC = ‘1’

activates the use of the CRC_TAG register at address 0x66

(see "CRC Tag (CRC_TAG) – Address 102" on page 50).

Step 3

Compute the CRC

Compute the CRC value of registers located at address 0x0 to

0x5F, including all factory-programmed registers and bits.

Write this calculated CRC value to the CRC_TAG register at

address 0x66.

Step 4

Initiate a Program Cycle

To enable OTP memory programming, the master needs to

write a Start condition followed by a slave address of 0x22 (7

MSB device address = ‘0010001’ and the LSB R/W = ‘0’ for a

write operation). Then a 0x79 (MSB BLK/SGL = ‘0’ and 7 LSB

0x73, ending the transmission with a Stop condition.

To initiate the program cycle, the master needs to write a Start

condition followed by a slave address of 0x22 (7 MSB device

address = ‘0010001’ and the LSB R/W = ‘0’ for a write

operation). Then a 0x72 (MSB BLK/SGL = ‘0’ and 7 LSB

0x90, ending the transmission with a Stop condition. The

program cycle takes approximately 35ms.

Step 5

Check OTP Program Status

To check if the program cycle completed successfully, the

master needs to write a Start condition followed by a slave

address of 0x23 (7 MSB device address = ‘0010001’ and the

LSB R/W = ‘1’ for a read operation). Then write a 0x59 (MSB

BLK/SGL = ‘0’ and 7 LSB register address = ‘1011001’). After

the acknowledge is received, the master needs to read the 8-

bit OTP Program Status register, ending the transmission with

a Stop condition.

If bit 4 of the Program Status register is set to ‘1’ then the OTP

write has finished. If bit 4 of the Program Status register is not

set to ‘1’, after the 35ms program cycle is complete, then a

CRC error likely occurred, or the program cycle was not

started properly.

Step 6

OTP Verification Check

Cycle the power to the CS1630/31. The OTP memory is

uploaded to the shadow registers. To check if the program

cycle was successful, the master needs to write a Start

condition followed by a slave address of 0x23 (7 MSB device

address = ‘0010001’ and the LSB R/W = ‘1’ for a read

operation). Then write a 0x7C (MSB BLK/SGL = ‘0’ and 7 LSB

received, the master needs to read the 8-bit OTP Verification

If the value in the 8-bit OTP Verification register is 0x01, then

the program process failed to execute properly. If the 8-bit

value is 0x00 then use a read operation to verify that the

values in the shadow registers match what was written to the

shadow registers in Step 1. If the values do not match, then it

is likely the OTP program process was not performed due to

an error when calculating the CRC or the CRC bit in the

Config38 register was not set to ‘1’. Verify that all bits read

from the shadow register match the bits prior to starting the

program process and start at Step 1 to perform the OTP

program process.

CS1630-FSZ 数据表(PDF) 26 Page - Cirrus Logic

CS1630-FSZ 数据表(HTML) 26 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载