CS1630-FSZ datasheet(37/56 Pages) APEX

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CS1630/31

DS954F2

6.20 Configuration 15 (Config15) – Address 47

6.21 Configuration 16 (Config16) – Address 48

654

EXIT_PH3

EXIT_PH2

EXIT_PH1

EXIT_PH0

DECL_PH3

DECL_PH2

DECL_PH1

DECL_PH0

Number

Name

Description

[7:4]

EXIT_PH[3:0]

Configures the number of channel 1 switching periods between phase syn-

chronization conditions on the second stage. EXIT_PH[3:0] provides a hyster-

esis to prevent consecutive resynchronizations by the controller. The value is

an unsigned integer in the range of 0

value15. EXIT_PH[3:0] needs to be

configured only for designs that use a dual channel synchronization circuit and

is not directly driven from the SYNC pin. The RESYNC bit must be enabled

(see “Configuration 17 (Config17) – Address 49” on page 38).

[3:0]

DECL_PH[3:0]

Configures the number of second stage switching periods with improper out-

put identification until the controller resynchronizes. There is a counter that

increments by 1 on improper output identification and decrements by 2 if

proper output identification is measured. If this counter exceeds the threshold

set by bits DECL_PH[3:0] and the controller has not seen a phase resynchro-

nization in EXIT_PH[3:0] cycles, the controller resynchronizes. The value is an

unsigned integer in the range of 0

value15. DECL_PH[3:0] needs to be con-

figured only for designs that use a dual channel synchronization circuit and is

not directly driven from the SYNC pin. The RESYNC bit must be enabled (see

“Configuration 17 (Config17) – Address 49” on page 38).

654

RE2_ZCD2

RE2_ZCD1

RE2_ZCD0

CH2_ZCD2

CH2_ZCD1

CH2_ZCD0

SCP

VDIFF

Number

Name

Description

[7:5]

RE2_ZCD[2:0]

Sets the fixed time delay TRE2ZCD(delay) for zero-current detection (ZCD) com-

parator to account for the delay on the rising edge of ZCD for channel 2. The

value is an unsigned integer in the range of 0

value7. The delay is defined

by:

[4:2]

CH2_ZCD[2:0]

Sets fixed time delay TCH2ZCD(delay) to account for the delay of the second

stage zero-current detection (ZCD) comparator during channel 2 switching

cycles when the voltage applied to the FBAUX pin falls below the 200mV ZCD

comparator threshold. Configuring TCH2ZCD(delay) is essential to achieve good

quasi-resonant (valley switching) performance. The value is an unsigned inte-

ger in the range of 0

value7. The delay is defined by:

[1]

SCP

Configures the second stage short circuit protection.

0 = Enable short circuit protection

1 = Disable short circuit protection

[0]

VDIFF

Configures the VDiff fault mechanism for use by the protection module.

0 = Enable VDiff fault

1 = Disable VDiff fault

TRE2ZCD delay



RE2_ZCD

[2:0] 50ns



TCH2ZCD delay



CH2_ZCD

[2:0] 50ns



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