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CS1630-FSZ 数据表(PDF) 33 Page - Cirrus Logic |
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CS1630-FSZ 数据表(HTML) 33 Page - Cirrus Logic |
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33 / 56 page ![]() CS1630/31 DS954F2 33 6.9 Configuration 4 (Config4) – Address 36 6.10 Second Stage Dim (S2DIM) – Address 37 S2DIM sets the minimum dim for second stage (flyback, buck, or tapped buck). The register value is an un- signed integer in the range of 0 value255. Enforced minimum dim percentage dimmin is determined by the following equation: 6.11 Maximum TT (TTMAX) – Address 38 TTMAX sets the maximum allowable target period for the second stage TT. The register value is an unsigned integer in the range of 0 value255. The maximum TT period is determined by: The maximum period for TT can be configured from 6.35 s to 1.63835ms. 7 654 32 10 T2CH1GAIN5 T2CH1GAIN4 T2CH1GAIN3 T2CH1GAIN2 T2CH1GAIN1 T2CH1GAIN0 SYNC POL_ZCD Number Name Description [7:2] T2CH1GAIN[5:0] Sets T2 compensation gain T2CH1CompGain for channel 1, which is required when T2 measurement compensation is enabled for flyback designs. The value is an unsigned integer in the range of 0 T2CH1GAIN[5:0]<63. Com- pensated T2 time T2Compensated used in the second stage charge regulation loop is given by: where, T2CH1CompGain is a decimal number in the range of 0.0T2CH1CompGain<4.0: [1] SYNC Enables the digital synchronization signal that indicates which channel the controller is signaling for each gate switching period on the IC’s SYNC pin. The SYNC bit should be enabled for non-isolated second stage designs where the synchronizer circuit is directly driven from the IC's SYNC pin. 0 = Disables SYNC onto pin 1 = Enables SYNC onto pin [0] POL_ZCD Sets polarity of zero-current detection comparator output. Recommended to set bit POL_ZCD to active-low polarity. 0 = Active-low polarity 1 = Positive polarity 7 654 32 10 27 26 25 24 23 22 21 20 7 654 32 10 27 26 25 24 23 22 21 20 T2Compensated T2 = Measured TZCD Ri gEdge sin T2CH1CompGain – T2CH1CompGain T2CH1GAIN[5:0] 0.0625 = dimmin S2DIM[7:0] 16 15 + 4095 -------------------------------------------------------- 100 = TTMAX[7:0] 128 127 + 50ns |
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