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CS1630-FSZ 数据表(PDF) 18 Page - Cirrus Logic |
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CS1630-FSZ 数据表(HTML) 18 Page - Cirrus Logic |
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18 / 56 page ![]() CS1630/31 18 DS954F2 Figure 20 illustrates the tapped buck stage configured for series output mode. Figure 20. Tapped Buck Series Output Model To maintain constant output current with minimum line- frequency ripple, the following are required: • For parallel configurations, a minimum voltage potential difference between two strings • For series configurations, a minimum current amplitude difference between two strings 5.8.2 Primary-side Current Control for Two-Channel Output The CS1630/31 regulates two-channel output current independently using primary-side control, which eliminates the need for opto-coupler feedback. The control loop operates in peak current control mode, with the peak current set cycle- by-cycle by the two independent current regulation loops. Demagnetization time of the second stage inductor is sensed by the FBAUX pin using an auxiliary winding on the second stage inductor. The FBAUX pin supplies an input to the digital control loop. The power conversion for two-channel output is carried out by interleaving the PWM. The two-channel control system consists of two components: • A toggle device (phase synchronizer circuit) on the secondary side that alternatively activates each output channel for each switching event • A digital sequencer on the primary side determines which output channel is active for any given switching event As the output is toggled between each channel, a sequencer on the primary side identifies the current control phase and regulates the current in each output channel. To ensure proper operation for a parallel configuration, the two output channels should target a voltage differential that is greater than 20%. For a series configuration, the two output channels should target a current differential that is greater than 20%. 5.8.3 Auxiliary Winding Configuration The second-stage inductor auxiliary winding is used for zero- current detection (ZCD) and overvoltage protection (OVP). The auxiliary winding is sensed through the FBAUX pin of the IC. 5.8.4 Control Parameters The second-stage control parameters are set to assure: • Line Regulation — The LED current remains constant despite a ±10% AC line voltage variation. • Effect of Variation in Transformer Magnetizing Inductance — The LED current remains constant over a ±20% variation in magnetizing inductance. The FBSENSE input is used to sense the current in the second stage inductor. When this current reaches a certain threshold, the gate drive turns ‘OFF’ (output on pin GD). Two OTP values are required to set the second-stage output currents, CH1CUR for channel 1 and CH2CUR for channel 2 (see "Channel 1 Output Current (CH1CUR) – Address 41" on page 35 and "Channel 2 Output Current (CH2CUR) – Address 43" on page 35). Equations 6 and 7 are used to calculate the values to be programmed into registers CH1CUR and CH2CUR. where, RSense = Resistance of current sense resistor VSense = Full scale voltage across sense resistor (~1.4V) ICH1 = Target current in channel 1 LED string ICH2 = Target current in channel 2 LED string RSense is determined by the input voltage, switching frequency, auxiliary transformer turns ratio, target output current and output voltage for each channel. The zero-current detect input on pin FBAUX is used to determine the demagnetization cycle T2. The controller then uses these inputs to control the gate drive output, GD. 5.8.5 Frequency Dithering The peak amplitude of switching harmonics can be reduced by spreading the energy into wider spectrums. The frequency dithering level can be managed using bits DITLEVEL[1:0] in register Config61 (see "Configuration 61 (Config61) – Address 93" on page 49). Additionally, the CS1630/31 has an option to enable dithering only in No-dimmer Mode by setting bit DITNODIM to ‘1’. If output currents differ, the CS1630/31 also has an option to allow for less dither on one of the two channels by selecting the channel using bit DITCHAN. The channel selected for less dither attenuates the dither level by the percentage configured by bits DITATT[1:0]. R13 R11 R14 Q4 L3 CS1630 /31 FBAUX GND 13 GD FBSENSE 15 12 11 VBST R12 D9 C9 R15 D10 R16 C10 Z3 D GND _ Q VCC Q5 IGND C12 LED1+ LED 1- C11 LED 2+ LED 2- D11 D8 CH1CUR 5112RSense ICH1 NVSense ---------------------------------------------------------- = [Eq.6] CH2CUR 5112RSense ICH2 NVSense ---------------------------------------------------------- = [Eq.7] |
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