CS1630-FSZ datasheet(46/56 Pages) APEX

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CS1630/31

DS954F2

6.36 Configuration 54 (Config54) – Address 86

654

LLP_TIME2

LLP_TIME1

LLP_TIME0 BOP_RSTART

Number

Name

Description

[7:5]

LLP_TIME[2:0]

Sets the time that the condition VBST < (VLine - VLLPMin(th)) is true to trigger a

boost LLP fault. See “Configuration 62 (Config62) – Address 94” on page 50

for configuring VLLPMin(th) using bits BST_LLP[1:0].

000 = 0ms

001 = 1ms

010 = 2ms

011 = 2.5ms

100 = 3ms

101 = 3.5ms

110 = 4ms

111 = 5ms

[4]

BOP_RSTART

Configures boost BOP fault behavior. When bit BOP_RSTART is set to ‘1’ the

IC attempts to restart after VBST drops down to a nominal voltage level. It is

recommended to enable bit MAX_CUR when BOP_RSTART = 1 so the sec-

ond stage can deliver full output power when a boost BOP fault is detected.

This helps quickly dissipate the energy stored in the boost output capacitor

bringing down the voltage on the capacitor.

0 = Latched fault

1 = Attempts to restart if VBST equals 195V for 120V application or 392V

for 230V application

[3:0]

Reserved

CS1630-FSZ 数据表(PDF) 46 Page - Cirrus Logic

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