ANSELA datasheet(143/222 Pages) MICROCHIP

143 / 222 page

 2013 Microchip Technology Inc.

DS22331A-page 143

MCP19111

26.1.4

PWM DUTY CYCLE (DCLOCK)

The PWM duty cycle (DCLOCK) is specified by writing

to the PWMRL register. Up to 8-bit resolution is

available. The following equation is used to calculate

the PWM duty cycle (DCLOCK):

EQUATION 26-4:

The PWMRL bits can be written to at any time, but the

duty cycle value is not latched into PWMRH until after

a match between PR2 and TMR2 occurs.

26.2

Operation during Sleep

When the device is placed in Sleep, the allocated

timer will not increment and the state of the module will

not change. If the CLKPIN pin is driving a value, it will

continue to drive that value. When the device wakes

up, it will continue from this state.

PWM DUTY CYCLE=PWMRL x TOSC x(T2 PRESCALE VALUE)

TABLE 26-1:

SUMMARY OF REGISTERS ASSOCIATED WITH PWM MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

APFCON

—

CLKSEL

110

T2CON

—

TMR2ON T2CKPS1 T2CKPS0

139

PR2

Timer2 Module Period Register

138*

PWMRL

PWM Register Low Byte

141*

PWMPHL

SLAVE Phase Shift Byte

141*

BUFFCON

MLTPH2

MLTPH1

MLTPH0

ASEL4

ASEL3

ASEL2

ASEL1

ASEL0

Legend:

— = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.

Page provides register information.

ANSELA 数据表(PDF) 143 Page - Microchip Technology

ANSELA 数据表(HTML) 143 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载