ANSELA datasheet(146/222 Pages) MICROCHIP

146 / 222 page

MCP19111

DS22331A-page 146

 2013 Microchip Technology Inc.

FIGURE 27-2:

MSSP BLOCK DIAGRAM (I2C SLAVE MODE)

27.2

I2C

MODE OVERVIEW

The Inter-Integrated Circuit Bus (I2C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment, where the master

devices initiate the communication. A Slave device is

controlled through addressing.

The MSSP module has eight registers for I2C

operation. They are the:

• MSSP Status Register (SSPSTAT)

• MSSP Control Register1 (SSPCON1)

• MSSP Control Register2 (SSPCON2)

• MSSP Control Register3 (SPPCON3)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

• MSSP Address Register (SSPADD)

• MSSP Address Register2 (SSPADD2)

• MSSP Address Mask Register1 (SSPMSK)

• MSSP Address Mask Register2 (SSPMSK2)

The SSPCON1 register is used to define the I2C mode.

Four selection bits (SSPCON1<3:0>) allow one of the

following I2C modes to be selected:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Master mode, clock = OSC/4 (SSPADD +1)

•I2C firmware controlled Master mode (Slave idle)

The SSPSTAT register gives the status of the data

transfer. This information includes detection of a

START or STOP bit, specifies if the data received byte

was data or address, if the next byte is completion of

the 10-bit address, and if this will be a read or write data

transfer.

The SSPBUF is the register to which transfer data is

written to or read from. The SSPSR register shifts the

data in or out of the device. In receive operation, the

SSPBUF and SSPSR create a double buffer receiver.

This allows reception of the next byte to begin before

reading the last byte of received data. When the

complete byte is received before the SSPBUF register

is read, a receiver overflow has occurred and the

SSPOV bit (SSPCON1<6>) is set and the byte in the

SSPSR is lost.

Read

Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and

Stop bit Detect

SSPBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT Reg)

SCL

SDA

Shift

Clock

MSb

LSb

SSPMSK Reg

ANSELA 数据表(PDF) 146 Page - Microchip Technology

ANSELA 数据表(HTML) 146 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载