ADV601

–45–

REV. 0

Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing

The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601’s direct registers, except the

Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are slower

than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct register, see

the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect Register

Data and Interrupt Mask/Status registers, your system MUST observe

ACK and RD or WR assertion timing.

Table XXXIII. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters

Parameter

Description

Min

Max

Unit

RD Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)

N/A

1

N/A

ns

RD Signal, Direct Register, Pulse Width Asserted (at 27 MHz VCLK)

N/A

1

N/A

ns

RD Signal, Direct Register, Pulse Width Deasserted (at 27 MHz VCLK)

5

N/A

ns

ADR Bus, Direct Register, Read Setup

2

N/A

ns

ADR Bus, Direct Register, Read Hold

2

N/A

ns

DATA Bus, Direct Register, Read Delay

N/A

171.6

2, 3

ns

DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)

13

N/A

ns

WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)

48.7

4

N/A

ns

ACK Signal, Direct Register, Read Delayed 27 MHz VCLK)

8.6

287.1

5, 6

ns

ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)

11

N/A

ns

NOTES

1

RD input must be asserted (low) until ACK is asserted (low).

VALID

VALID

VALID

VALID

(I) ADR,

BE, CS

(I)

RD

(O) DATA

(O)

ACK

(I)

WR

t

ADR_D_RDS

t

ACK_D_RDOH

t

RD_D_RDC

t

RD_D_PWA

t

RD_D_PWD

t

ADR_D_RDH

t

DATA_D_RDD

t

DATA_D_RDOH

t

RD_D_WRT

t

ACK_D_RDD

Figure 37. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing