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ADV601

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DSP Interface Pins (Continued)

Name

Pins

I/O

Description

Serial Transmit Frame Sync. Connect this pin to an optional, external DSP’s serial

interface RF Sync pin. If no DSP is present, leave this pin unconnected. This pin is

compatible with 30 pF loads.

The TF pin is the transmit frame synch. When transmitting, the ADV601 marks

new frames with a HI pulse driven out on TF one serial clock period before the

frame begins. Whether transmitting or receiving, the synch signals may transition

back from HI to LO at any time, provided the HI and LO times of TF or RF are at

least one TCLK period in duration. Note that the DSP must be set for external

framing on receive data. Frame size for ADV601 serial data transmission is 52 slots

of 16 bits.

Note that the Mode Control register must be set to indicate whether or not the

external DSP is present.

Receive Frame Sync. Connect this pin to an optional, external DSP’s serial inter-

face TF Sync pin. If no DSP is present, tie this pin to ground. This pin is compat-

ible with 30 pF loads.

The RF pin is the receive frame synch. When receiving, the ADV601 requires that

the DSP marks new frames with a LO to HI transition driven in on RF one serial

clock period before the frame begins. Whether transmitting or receiving, the synch

signals may transition back from HI to LO at any time provided the HI and LO

times of TF or RF are at least one TCLK period in duration. Note that the DSP

must be set for internal framing on transmit data. When receiving, the frame size

for ADV601 serial data is 84 slots of 16 bits.

Note that the Mode Control register must be set to indicate whether or not the

external DSP is present.

DIRQ

DSP Interrupt. Connect this pin to an optional, external DSP’s hardware interrupt

pin (IRQ2). If no DSP is present, this pin may be left unconnected. This pin is

compatible with 30 pF loads.

The

DIRQ pin on the ADV601 provides an optional method for signalling the DSP

that a new packet of field statistics is being transmitted and can be used system-

wide for signalling that a new video field has begun. Because the ADV601 asserts

DIRQ throughout statistics transmission and bin width reception, the DSP’s inter-

rupts should be set for edge-sensitivity.

Note that the Mode Control register must be set to indicate whether or not the

external DSP is present.

Host Interface Pins

Name

Pins

I/O

Description

DATA[31:0]

I/O

Host Data Bus. These pins make up a 32-bit wide host data bus. The host controls

this asynchronous bus with the

WR, RD, BE, and CS pins to communicate with

the ADV601. These pins are compatible with 30 pF loads.

ADR[1:0]

Host DWord Address Bus. These two address pins let you address the ADV601’s

four directly addressable host interface registers. For an illustration of how this

addressing works, see the Control and Write Register Map figure and Status and

Read Register Map figure. The ADR bits permit register addressing as follows:

ADR1

ADR0

DWord

Address Byte Address

0x00

0x04

0x08

0x0C

BE0–BE3

Host Byte Enable pins. These four input pins allow selection of which bytes in

ADV601 direct and indirect registers will be accessed through the Host Interface;

BE0—least significant byte BE3—most significant byte. For a 32-bit interface only,

tie these pins to ground, making all bytes available.

ADV601JS 数据表(PDF) 18 Page - Analog Devices

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ADV601JS 数据表(PDF) 18 Page - Analog Devices

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