ADV601JS datasheet(37/52 Pages) AD

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ADV601

–37–

REV. 0

TIMING PARAMETERS

This section contains signal timing information for the ADV601. Timing descriptions for the following items appear in this

section:

• Clock signal timing

• Video data transfer timing (CCIR-656, Gray Scale/Philips, and Multiplexed Philips formats)

• Host data transfer timing (direct register read/write access)

• DSP data transfer (serial data transfer)

Clock Signal Timing

The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin

loading of 50 pF.

Table XX. Video Clock Period, Frequency, Drift and Jitter

Min VCLK_CYC

Nominal VCLK_CYC

Max VCLK_CYC

Video Format

Period

Period (Frequency)

Period

1, 2

CCIR-601 PAL

35.2 ns

37 ns (27 MHz)

38.9 ns

Square Pixel PAL

32.2 ns

33.89 ns (29.5 MHz)

35.5 ns

CCIR-601 NTSC

35.2 ns

37 ns (27 MHz)

38.9 ns

Square Pixel NTSC

38.7 ns

40.75 ns (24.54 MHz)

42.7 ns

NOTES

1VCLK Period Drift =

± 0.1 (VCLK_CYC/field.

2VCLK edge-to-edge jitter = 1 ns.

Table XXI. Video Clock Duty Cycle

Min

Nominal

Max

VCLK Duty Cycle

(40%)

(50%)

(60%)

NOTE

1VCLK Duty Cyle = t

VCLK_HI/(tVCLK_LO) × 100.

Table XXII. Video Clock Timing Parameters

Parameter

Description

Min

Max

Unit

tVCLK_CYC

VCLK Signal, Cycle Time (1/Frequency) at 27 MHz

(See Video Clock Period Table)

tVCLKO_D0

VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz

tVCLKO_D1

VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz

TEST CONDITIONS

Figure 23 shows test condition voltage reference and device

loading information. These test conditions consider an output

as disabled when the output stops driving and goes from the

measured high or low voltage to a high impedance state. Tests

measure output disable time (tDISABLE) as the time between the

reference input signal crossing +1.5 V and the time that the

output reaches the high impedance state (also +1.5 V). Simi-

larly, these tests conditions consider an output as enabled when

the output leaves the high impedance state and begins driving a

measured high or low voltage. Tests measure output enable time

(tENABLE) as the time between the reference input signal crossing

+1.5 V and the time that the output reaches the measured high

or low voltage.

INPUT

REFERENCE

SIGNAL

OUTPUT

SIGNAL

DISABLED

ENABLED

1.5V

VOH

VOL

VIH

VIL

1.5V

INPUT & OUTPUT VOLTAGE/TIMING REFERENCES

DEVICE LOADING FOR AC MEASUREMENTS

OUTPUT

2pF

+1.5V

IOL

IOH

Figure 23. Test Condition Voltage Reference and Device Loading

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