ADV601

–14–

REV. 0

Compression Ratio Register

Indirect (Write Only) Register Index 0x06

This register holds the value that is used by the DSP to control compression during encode mode. Note that this register should only

be used when a DSP is calculating Bin Widths.

[7:0]

Compression Ratio, CRA[7:0]. Value passed to the DSP during encode operation. The 8-bit value in this field is sent to the

DSP through the serial interface during DSP-assisted encode operations. CRA values are zero-filled from the MSB and one

each is sent to the DSP as part of the packet of data on which the ratio is applied. The DSP software uses the CRA value

and other statistics to calculate BW controls for the ADV601’s quantizer. Note that the relationship between CRA and the

actual compression ratio is dependent on the BW control algorithm used in the DSP (undefined at reset).

[15:8]

Reserved (always write zero)

Sum of Squares [0–41] Registers

Indirect (Read Only) Register Index 0x080 through 0x0A9

The Sum of Squares [0–41] registers hold values that correspond to the summation of values (squared) in corresponding Mallat

blocks [0–41]. These registers let the Host or DSP read sum of squares statistics from the ADV601; using these values (with the Sum

of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV601 indicates that

the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the statistics at

any time. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.

[15:0]

Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square

values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for

large blocks. The 16-bit codes have the following precision:

Blocks Precision

Sum of Squares Precision Description

0–2

48.–32

48.-bits wide, left shift code by 32-bits, and zero fill

3–11

46.–30

46.-bits wide, left shift code by 30-bits, and zero fill

12–20

44.–28

44.-bits wide, left shift code by 28-bits, and zero fill

21–29

42.–26

42.-bits wide, left shift code by 26-bits, and zero fill

30–41

40.–24

40.-bits wide, left shift code by 24-bits, and zero fill

If the Sum of Squares code were 0x0025 for block 10, the actual value would be 0x000940000000; if using that same

code, 0x0025, for block 30, the actual value would be 0x0025000000.

[31:0]

Reserved (always read zero)

Sum of Luma Value Register

Indirect (Read Only) Register Index 0x0AA

The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The Host

reads these values through the Host Interface or the DSP receives these values through the serial port.

[15:0]

Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset)

[31:0]

Reserved (always read zero)

Sum of Cb Value Register

Indirect (Read Only) Register Index 0x0AB

The Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. The Host reads

these values through the Host Interface or the DSP receives these values through the serial port.

[15:0]

Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset)

[31:0]

Reserved (always read zero)

Sum of Cr Value Register

Indirect (Read Only) Register Index 0x0AC

The Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. The Host reads

these values through the Host Interface or the DSP receives these values through the serial port.

[15:0]

Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset)

[31:0]

Reserved (always read zero)