ADV601

–49–

REV. 0

DSP Interface Timing

The diagram in this section shows transfer timing for one set of video statistics and calculated bin widths as they pass through the

ADV601’s DSP interface. Whenever an ADV601’s serial port is inactive, the codec’s TXD pin is three-stated and the codec ignores

the state of the RXD pin. Figure 41 illustrates the ADV601 serial interface’s signal, sample and frame relationships for the transmit

and receive modes.

Table XXXVII. DSP Read and Write Transfer Timing Parameters

Parameter

Description

Min

Max

Unit

DIRQ Signal, Transfer-Receive Cycle Start, Delay

N/A

4

ns

DIRQ Signal, Transfer-Receive Cycle End, Output Hold

3

N/A

ns

TCLK Signal, Referenced to VCLK, Delay

N/A

11

ns

TF Signal, Transfer Frame Reference to TCLK, Delay

N/A

3

ns

TF Signal, Transfer Frame Reference to TCLK, Output Hold

2

N/A

ns

TXD Sample, Transfer Data, Delay (at 27 MHz VCLK)

N/A

24.2

1

ns

TXD Sample, Transfer Data, Output Hold

2

N/A

ns

RF Signal, Receive Frame Referenced to TCLK, Setup

2

N/A

ns

RF Signal, Receive Frame Referenced to TCLK, Hold

105

N/A

ns

RXD Sample, Receive Data, Setup

2

N/A

ns

RXD Sample, Receive Data, Hold (at 27 MHz VCLK)

16.8

2

N/A

ns

NOTES

(O)

DIRQ

DSP CALCULATES BIN WIDTHS

FROM VIDEO STATISTICS

(I) VCLK

(O) TCLK

TCLK PERIOD = 4

FIFTY-TWO 16-BIT WORDS TRANSFERRED BY THE ADV601

-- ADV601 REGISTERS 0x06 AND 0x80 THROUGH 0xB2

EIGHTY-FOUR 16-BIT WORDS TRANSFERRED BY THE DSP

-- ADV601 REGISTERS 0x100 THROUGH 0x153

(O) TF

(O) TXD

t

TCLK_TXD_OH

t

TCLK_TXD_D

t

TCLK_RF_S

t

TCLK_RXD_H

t

TCLK_RXD_S

(I) RF

(I) RXD

t

TCLK_DIRQ_OH

t

TCLK_DIRQ_D

t

TCLK_TF_D

t

VCLK_TCLK_D

t

TCLK_RF_H

t

TCLK_TF_OH

Figure 41. DSP Read and Write Transfer Timing