数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADV601JS 数据表(PDF) 46 Page - Analog Devices

部件名 ADV601JS
功能描述  Low Cost Multiformat Video Codec
PDF  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV601JS 数据表(HTML) 46 Page - Analog Devices

Back Button ADV601JS Datasheet HTML 42Page - Analog Devices ADV601JS Datasheet HTML 43Page - Analog Devices ADV601JS Datasheet HTML 44Page - Analog Devices ADV601JS Datasheet HTML 45Page - Analog Devices ADV601JS Datasheet HTML 46Page - Analog Devices ADV601JS Datasheet HTML 47Page - Analog Devices ADV601JS Datasheet HTML 48Page - Analog Devices ADV601JS Datasheet HTML 49Page - Analog Devices ADV601JS Datasheet HTML 50Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 46 / 52 page
background image
ADV601
–46–
REV. 0
Table XXXIV. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters
Parameter
Description
Min
Max
Unit
tWR_D_WRC
WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK)
N/A
1
N/A
ns
tWR_D_PWA
WR Signal, Direct Register, Pulse Width Asserted (at 27 MHz VCLK)
N/A
1
N/A
ns
tWR_D_PWD
WR Signal, Direct Register, Pulse Width Deasserted (at 27 MHz VCLK)
5
N/A
ns
tADR_D_WRS
ADR Bus, Direct Register, Write Setup
2
N/A
ns
tADR_D_WRH
ADR Bus, Direct Register, Write Hold
2
N/A
ns
tDATA_D_WRS
DATA Bus, Direct Register, Write Setup
–20
N/A
ns
tDATA_D_WRH
DATA Bus, Direct Register, Write Hold
0
N/A
ns
tWR_D_RDT
WR Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)
35.6
2
N/A
ns
tACK_D_WRD
ACK Signal, Direct Register, Write Delay (at 27 MHz VCLK)
8.6
182.1
3, 4
ns
tACK_D_WROH
ACK Signal, Direct Register, Write Output Hold
11
N/A
ns
NOTES
1
WR input must be asserted (low) until ACK is asserted (low).
2Minimum t
WR_D_RDT varies with VCLK according to the formula: t WR_D_RDT (MIN) = 0.8 (VCLK Period) +7.4.
3Maximum t
WR_D_WRD varies with VCLK according to the formula: t ACK_D_WRD (MAX) = 4.3 (VCLK Period) +14.8.
4During STATS_R deasserted (low) conditions, t
ACK_D_WRD may be as long as 52 VCLK periods.
VALID
VALID
VALID
VALID
(I) ADR,
BE, CS
(I)
WR
(I) DATA
(O)
ACK
(I)
RD
t
ADR_D_WRS
t
DATA_D_WRS
t
ACK_D_WROH
t
WR_D_WRC
t
WR_D_PWA
t
WR_D_PWD
t
ADR_D_WRH
t
DATA_D_WRH
t
ACK_D_WRD
t
WR_D_RDT
Figure 38. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com