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ADV601JS 数据表(PDF) 48 Page - Analog Devices |
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ADV601JS 数据表(HTML) 48 Page - Analog Devices |
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48 / 52 page ![]() ADV601 –48– REV. 0 Table XXXVI. Host (Compressed Data) Write Timing Parameters Parameter Description Min Max Unit tWR_CD_WRC WR Signal, Compressed Data Direct Register, Write Cycle time 28 N/A ns tWR_CD_PWA WR Signal, Compressed Data Direct Register, Pulse Width Asserted 10 N/A ns tWR_CD_PWD WR Signal, Compressed Data Direct Register, Pulse Width Deasserted 10 N/A ns tADR_CD_WRS ADR Bus, Compressed Data Direct Register, Write Setup 2 N/A ns tADR_CD_WRH ADR Bus, Compressed Data Direct Register, Write Hold 2 N/A ns tDATA_CD_WRS DATA Bus, Compressed Data Direct Register, Write Setup 2 N/A ns tDATA_CD_WRH DATA Bus, Compressed Data Direct Register, Write Hold 2 N/A ns tACK_CD_WRD ACK Signal, Compressed Data Direct Register, Write Delay N/A 19 ns tACK_CD_WROH ACK Signal, Compressed Data Direct Register, Write Output Hold 9 N/A ns (I) ADR, BE, CS (I) WR (I) DATA (O) ACK VALID t ADR_CD_WRH t ADR_CD_WRS t DATA_CD_WRS t DATA_CD_WRH t ACK_CD_WRD t WR_CD_WRC t ACK_CD_WROH VALID VALID VALID t WR_CD_PWA t WR_CD_PWD Figure 40. Host (Compressed Data) Write Transfer Timing |
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