ADV601

–47–

REV. 0

Host Interface (Compressed Data) Register Timing

The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac-

cesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt

Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address, Indirect

Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the

RD or WR

signal assertion timing, your system does NOT have to wait for the

ACK signal between new compressed data addresses.

Table XXXV. Host (Compressed Data) Read Timing Parameters

Parameter

Description

Min

Max

Unit

RD Signal, Compressed Data Direct Register, Read Cycle Time

28

N/A

ns

RD Signal, Compressed Data Direct Register, Pulse Width Asserted

10

N/A

ns

RD Signal, Compressed Data Direct Register, Pulse Width Deasserted

10

N/A

ns

ADR Bus, Compressed Data Direct Register, Read Setup

2

N/A

ns

ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)

2

N/A

ns

DATA Bus, Compressed Data Direct Register, Read Delay

N/A

10

ns

DATA Bus, Compressed Data Direct Register, Read Output Hold

18

N/A

ns

ACK Signal, Compressed Data Direct Register, Read Delay

N/A

18

ns

ACK Signal, Compressed Data Direct Register, Read Output Hold

9

N/A

ns

(I) ADR,

BE, CS

(I)

RD

(O) DATA

(O)

ACK

VALID

VALID

VALID

VALID

t

ADR_CD_RDS

t

DATA_CD_RDD

t

ACK_CD_RDD

t

ACK_CD_RDOH

t

DATA_CD_RDOH

t

ADR_CD_RDH

t

RD_CD_RDC

t

RD_CD_PWA

t

RD_CD_PWD

Figure 39. Host (Compressed Data) Read Transfer Timing