ADV601

–12–

REV. 0

[5]

Video Interface Master/Slave Mode Select, M/S. This bit selects the following:

0

Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value

1

Master mode video interface (ADV601 controls video timing, HSYNC-VSYNC are outputs)

[6]

Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:

0

525 mode video interface, reset value

1

625 mode video interface

[7]

Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:

0

Decode mode video interface (compressed-to-raw)

1

Encode mode video interface (raw-to-compressed), reset value

[8]

Video Interface Square Pixel Mode Enable, SPE. This bit selects the following:

0

Disable Square Pixel mode video interface

1

Enable Square Pixel mode video interface, reset value

[9]

Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:

0

Bipolar color component mode video interface, reset value

1

Unipolar color component mode video interface

[10]

External DSP Select for bin width calculations, DSP. This bit selects the following:

0

Host provides bin width calculation, reset value

1

External DSP provides bin width calculation

[11]

Video Interface Software Reset, SWR. This bit has the following effects on ADV601 operations:

0

Normal operation

1

Software Reset. This bit is set on hardware reset and must be cleared before the ADV601 can begin processing. (reset value)

When this bit is set during encode, the ADV601 completes processing the current field then suspends operation until the

SWR bit is cleared. When this bit is set during decode, the ADV601 suspends operation immediately and does not resume

operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed.

[12]

HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV601 operations:

0

HSYNC is HI during blanking, reset value

1

HSYNC is LO during blanking (HI during active)

[13]

HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV601 operations:

0

HIRQ is active LO, reset value

1

HIRQ is active HI

[15:14] Reserved (always write zero)

FIFO Control Register

Indirect (Read/Write) Register Index 0x01

This register holds the service-request settings for the ADV601’s host interface FIFO, causing interrupts for the “nearly full” and

“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by

32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV601

uses these setting to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).

[3:0]

Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condi-

tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is

512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the

register and their meaning.

ESL Interrupt When . . .

0000 Disables service requests (FIFO_SRQ never goes HI during encode)

0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)

1000 FIFO is 1/2 full, reset value

1111 FIFO has only 32 positions empty (480 positions filled)

[7:4]

Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a

condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO

is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the

register and their meaning.

DSL Interrupt When . . .

0000 Disables service requests (FIFO_SRQ never goes HI)

0001 FIFO has only 32 positions filled (480 positions empty)

1000 FIFO is 1/2 empty, reset value

1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)

[15:8]

Reserved (always write zero)