ADV601

–10–

REV. 0

ADV601 REGISTER DESCRIPTIONS

Indirect Address Register

Direct (Write) Register Byte Offset 0x00.

This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All

indirect write registers are 16-bits wide. The address in this register is auto-incremented on each subsequent access of the indirect

data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.

In 8-bit mode, auto-increment occurs after writing to Byte 1 (

BE1 pin asserted) of the Indirect Data Register; always read or write

Byte 0 then Byte 1 when in 8-bit mode.

[15:0]

Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through

the indirect data register (undefined at reset)

[31:16] Reserved (undefined read/write zero)

Indirect Register Data

Direct (Read/Write) Register Byte Offset 0x04

This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register. In 8-bit

mode, Byte 0 is read or written first followed by Byte 1. This ensures correct operation of auto-increment.

[15:0]

Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.

[31:16] Reserved (undefined read/write zero)

Compressed Data Register

Direct (Read/Write) Register Byte Offset 0x08

This register holds a 32-bit sequence from the compressed video bit stream. This register is buffered by a 512 position, 32-bit FIFO.

Access bytes in the following order for correct auto-increment: Byte 0, Byte 1, Byte 2, then Byte 3. For Word (16-bit) accesses, ac-

cess Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3). For a description of the data sequence, see the Compressed

Data Stream Definition section.

[31:0]

Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.

Interrupt Mask / Status Register

Direct (Read/Write) Register Byte Offset 0x0C

This 16-bit register contains interrupt mask and status bits that control the state of the ADV601’s

HIRQ pin. With the seven mask

bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the conditions that

are ORed together to determine the output of the

HIRQ pin.

Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are

sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the

condition coming true, they cannot be read or tested for stable level true conditions multiple times.

The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by

using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.

[0]

CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:

0

No CCIR-656 Error condition, reset value

1

Unrecoverable error in CCIR-656 data stream (missing sync codes)

[1]

Statistics Ready, STATSR. This read only status bit indicates the following:

0

No Statistics Ready condition, reset value (STATS_R pin LO)

1

Statistics Ready for BW calculator (STATS_R pin HI)

[2]

Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be

retrieved from the FIFO on the next read from the host bus.

0

No Last Code condition, reset value (LCODE pin LO)

1

Next read retrieves last word for field in FIFO (LCODE pin HI)

[3]

FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:

0

No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)

1

FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)