ADV601JS datasheet(34/52 Pages) AD

34 / 52 page

ADV601

–34–

REV. 0

The Bt819A has a horizontal scaling function that is used to

implement the decimation from the 8xFsc rate to the required

number of pixels per scan line (Pdesired). The value that must

be programmed is HSCALE.

• HSCALE = ((910/Pdesired) – 1)

× 4096 {for NTSC}

• HSCALE = ((1135/Pdesired) – 1)

× 4096 {for PAL}

Note that the circuit in Figure 17 has not been built or tested.

VCLKO

RDEN

Bt819A

VDATA (15:0)

CLKIN

XTO & XT1

VCLKO

CREF

VDATA (9:2,19:12)

ADV601

8xFSC

VCLK0

FIELD

HSYNC

VSYNC

ACTIVE

VCLK

DVALID

(API MODE B)

(PHILIPS & SLAVE MODE)

FIELD

Figure 17. ADV601 and Bt819A Example Interfacing Block

Diagram

Using the Philips SAA7110 or SAA 7111 Video Decoder

The SAA7110 can only be used with Square Pixel sample rates.

Note that the circuit in Figure 18 has not been built or tested.

XTAL

(PHILIPS & SLAVE MODE)

CREF

HREF

ODD

SAA7110

Y(0:7),UV(0:7)

LLC

XTAL

VCLK

CREF

VSYNC

HSYNC

VDATA (2:9,12:19)

FIELD

ADV601

Figure 18. ADV601 and SAA7110 Example Interfacing

Block Diagram

The SAA7111 example circuit, which appears in Figure 19, is

used in this configuration on the ADV601 Video Lab demon-

stration board.

XTAL

(CCIR-656 MODE)

CREF

SAA7111

Y(0:7),UV(0:7)

LLC

XTAL

VCLK

CREF

VDATA (2:9,12:19)

ADV601

Figure 19. ADV601 and SAA7111 Example Interfacing

Block Diagram

Using the Analog Devices ADV7175 Video Encoder

Because the ADV7175 has a CCIR-656 interface, it connects

directly with the ADV601 without “glue” logic. Note that the

ADV7175 can only be used at CCIR-601 sampling rates.

The ADV7175 example circuit, which appears in Figure 20, is

used in this configuration on the ADV601 Video Lab demon-

stration board.

(MODE 0 & SLAVE MODE)

(CCIR-656 MODE)

XTAL

10k

Ω

150

Ω

VCLK

XTAL

ADV601

VCLKO

CLOCK

P7–P0

ADV7175

BLANK

ALSB

VDATA (9:2)

Figure 20. ADV601 and ADV7175 Example Interfacing

Block Diagram

Using the Raytheon TMC22173 Video Decoder

Raytheon has a whole family of video parts. Any member of the

family can be used. The user must select the part needed based

on the requirements of the application. Because the Raytheon

part does not include the A/Ds, an external A/D is necessary in

this design (or a pair of A/Ds for S video).

The part can be used in CCIR-656 (D1) mode for a zero con-

trol signal interface or can be used with the more traditional

HSYNC, VSYNC and FIELD signals used for a Philips style

interface. Special attention must be paid to the video output

modes in order to get the right data to the right pins (see the

following two diagrams).

Note that the circuits in Figure 21 and Figure 22 have not been

built or tested.

(PHILIPS & SLAVE MODE)

MODE SET TO:

CDEC = 1

YUVT = 0

F422

= 1

LDV

DVSYNC

FID(0)

TMC22153

Y(0:9),U(0:9)

CLOCK

XTAL

DHSYNC

VCLK

CREF

VCLK

HSYNC

VDATA (0:9,10:19)

FIELD

ADV601

VSYNC

VCLKOUT

Figure 21. ADV601 and TMC22153 Example Philips-Like

Mode Interface

MODE SET TO:

CDEC = 1

YUVT

= 1

F422

= X

TMC22153

Y(0:9)

CLOCK

XTAL

VCLK

VDATA (0:9)

ADV601

(CCIR656 & SLAVE MODE)

Figure 22. ADV601 and TMC22153 Example CCIR-656

Mode Interface

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