STM32F303VC datasheet(113/133 Pages) STMICROELECTRONICS

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STM32F302xx/STM32F303xx

Electrical characteristics

Doc ID 023353 Rev 5

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Figure 34.

12-bit buffered /non-buffered DAC

The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

tSETTLING

(3)

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±1LSB

-3

µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

Update

rate(3)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

tWAKEUP

(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and

highest possible ones.

PSRR+ (1)

Power supply rejection ratio

(to VDDA) (static DC

measurement

–67

–40

dB No RLOAD, CLOAD = 50 pF

Guaranteed by design, not tested in production.

Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is

involved.

Data based on characterization results, not tested in production.

Table 70.

DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

R LOAD

C LOAD

Buffered/Non-buffered DAC

DACx_OUT

Buffer(1)

12-bit

digital to

analog

converter

ai17157

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