EPF10K100 datasheet(120/128 Pages) ALTERA

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120

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes:

(1)

To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the

input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this

frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency

during device operation. Simulation does not reflect this parameter.

(2)

During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If

the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during

configuration, because the tLOCK value is less than the time required for configuration.

(3)

The tJITTER specification is measured under long-term observation.

Power

Consumption

The supply power (P) for FLEX 10K devices can be calculated with the

following equation:

P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO

Typical ICCSTANDBY values are shown as ICC0 in the FLEX 10K device DC

operating conditions tables on pages 46, 49, and 52 of this data sheet. The

ICCACTIVE value depends on the switching frequency and the application

logic. This value is calculated based on the amount of current that each LE

typically consumes. The PIO value, which depends on the device output

load characteristics and switching frequency, can be calculated using the

guidelines given in Application Note 74 (Evaluating Power for Altera Devices).

Compared to the rest of the device, the embedded array

consumes a negligible amount of power. Therefore, the

embedded array can be ignored when calculating supply

current.

The ICCACTIVE value is calculated with the following equation:

ICCACTIVE = K × fMAX × N × togLC ×

The parameters in this equation are shown below:

fCLKDEV1 Input deviation from user specification in MAX+PLUS II (ClockBoost clock

multiplication factor equals 1) (1)

±1MHz

fCLKDEV2 Input deviation from user specification in MAX+PLUS II (ClockBoost clock

multiplication factor equals 2) (1)

±0.5

MHz

tINCLKSTB Input clock stability (measured between adjacent clocks)

100

tLOCK

Time required for ClockLock or ClockBoost to acquire lock (2)

µs

tJITTER

Jitter on ClockLock or ClockBoost-generated clock (3)

1ns

tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock

Table 113. ClockLock & ClockBoost Parameters

(Part 2 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

µA

MHz

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EPF10K100 数据表(PDF) 120 Page - Altera Corporation

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