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Functional Description (Continued)

3.2.3

Timing Signals

The CS9211 provides features that allow control over the

timing pulses coming from the CS550A (or other source)

and over those which drive the panel. These pulses may be

inverted, positioned, and otherwise modified as explained

in this section.

3.2.3.1

Input Timing Signals

The internal logic of the CS9211 is designed to operate

from the leading edge of the incoming VSYNC and HSYNC

pulses. This internal logic is triggered from the rising edge

of the input pulses after inversion (or not) by Offset 400h

bits 30 and 29, as shown in Figure 3-7. The purpose of the

Offset 400h[30:29] is to make the leading edge of the input

pulses (be it a rising or falling edge) appear as a rising

edge to the internal logic, thereby triggering the internal

logic at the leading edge of the input pulses. In Figure 3-7,

when the FP_xSYNC_POL bit is 1 (POL = 1), the inverting

buffer will be enabled; when the FP_xSYNC_POL bit is 0

(POL = 0), the non-inverting buffer will be enabled. (The

terminology FP_xSYNC_POL refers to the fact that this

holds true for both the HSYNC and VSYNC pulses).

Two bits (Offset 400h[30:29]) are used to match the

CS9211 to the polarity of the incoming HSYNC and

VSYNC signals, as shown in Table 3-5. These bits should

be set as indicated to match the polarity of the incoming

timing pulses to the CS9211’s internal logic needs.

The internal logic following the HSYNC input may be

bypassed by programming Offset 400h[27] = 0. In this

case, the input HSYNC, after possible inversion by Offset

400[29], is passed directly onto the output pin of the

CS9211. If Offset 400h[27] = 1, then the incoming HSYNC

pulse may be modified by Offset 400h[7:0] before being

passed to the output HSYNC pin.

Figure 3-7. Input Timing Pulse Polarity Selection

Internal

Logic

Sync

Leading Edge

POL = 1

POL = 0

Input

Table 3-5. Input Timing Control Bits

Bit

Name

Description

Offset 400h-403h

Panel Timing Register 1 (R/W)

Reset Value = 0000000h

FP_VSYNC_POL

FP_VSYNC Input Polarity: Selects positive or negative polarity of the FP_VSYNC input (pin 99).

Program this bit to match the polarity of the incoming FP_VSYNC signal. Note that bit 23 of Offset

404h independently controls the polarity of the output VSYNC.

0 = FP_VSYNC is normally low, transitioning high during sync interval (Default).

1 = FP_VSYNC is normally high, transitioning low during sync interval.

FP_HSYNC_POL

FP_HSYNC Input Polarity: Selects positive or negative polarity of the FP_HSYNC input (pin 97).

Program this bit to match the polarity of the incoming FP_HSYNC signal. Note that bit 22 of Offset

404h independently controls the polarity of the output HSYNC.

0 = FP_HSYNC is normally low, transitioning high during sync interval (Default).

1 = FP_HSYNC is normally high, transitioning low during sync interval.

HSYNC_SRC

TFT Horizontal Sync Source: Selects an internally generated or external pass-through source of

the TFT horizontal sync output on pin 31. The internally generated HSYNC pulse will be triggered by

the input HSYNC, but the output polarity, and leading and trailing edge positions are controlled by

registers 404h[22] and 400h[7:0] respectively. The external mode will pass the input HSYNC pulse

directly to the output pin.

0 = Pass the input HSYNC directly onto the output LP/HSYNC pin (pin 31) (Default).

1 = Internally generate the output HSYNC using the leading/trailing edge bits [7:0] and the polarity

bit (Offset 404h[22]).

7:5

HSYNC_LEADING_

EDGE

Horizontal Sync Leading Edge Position: Selects the position of the leading edge of the output

HSYNC pulse with respect to the rising edge of the modified input HSYNC pulse. The modified input

HSYNC pulse is that which has been inverted, or not inverted, by bit 29. The position is programma-

ble in steps of 1 DOTCLK, starting at 2 DOTCLOCKS and extending up to 8. Bit 27 must be set in

order for bits [7:5] to be recognized. Note that there are combinations of bits [7:5] and [4:0] that can

result in a zero- or negative-length pulse, for example if the trailing edge is positioned before the

leading edge. In this case, the output pulse will not be generated.

000 = No delay from the input HSYNC (Default).

001-111 = Position the HSYNC leading edge by 2 to 8 DOTCLKs with respect to the input HSYNC

rising edge. Note that there is no setting for a position of 1 DOTCLOCK.

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