CS9211 datasheet(45/62 Pages) NSC

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0DITH_ENB

Dithering Enable: Enable/disable dithering. The dither bit must be enabled in order for dither RAM

reads or writes to occur. When this bit is cleared, the internal dither RAM is powered down.

0 = Dither disable - The dithering function is turned off. When the dither is disabled, dither bits [3:1] do

not have any effect and the dither RAM is not accessible.

1 = Dither enable. The dither functions with the number of dither bits as set in [3:1]

Offset 410h-413h

BLUE LFSR SEED Register (R/W)

Reset Value = 00000000h

31:15

RSVD

Reserved: These bits are not defined.

14:0

BSEED

Blue LFSR Seed[14:0]: 15-bit value that specifies the seed value for the FRM conversion of the Blue

component of each pixel

Offset 414h-417h

Red and Green LFSR Seed Register (R/W)

Reset Value = 00000000h

RSVD

Reserved: This bit is not defined.

30:16

GSEED

Green LFSR Seed[14:0]: 15-bit value that specifies the seed value for the FRM conversion of the

Green component of each pixel

RSVD

Reserved: This bit is not defined.

14:0

RSEED

Red LFSR Seed[14:0]: 15-bit value that specifies the seed value for the FRM conversion of the Red

component of each pixel

Offset 418h-41Bh

FRM Memory Index Register (R/W)

Reset Value = 00000000h

31:10

RSVD

Reserved: These bits are not defined.

9:8

RGB_SEL

RGB Memory (FRM RAM) Select: Allows reading or writing to individual R,G, and B memory FRM

RAM locations or writing to all of them at the same time.

00 = Read from R FRM RAM but write to RGB FRM RAM.

01 = read or write to R FRM RAM.

10 = Read or write to G FRM RAM.

11 = Read or write to B FRM RAM.

Note: All FRM RAMs can be accessed through the serial interface before the panel is powered up.

7:6

RSVD

Reserved: These bits are not defined.

5:0

FRM_INDEX

FRM Memory Index: This auto-incrementing value represents the index to the FRM RAM. Each RAM

is configured as 32x64, requiring two index values to update each row of FRM RAM.

For example, the 00h index value will update the 32 LSB’s of row “0” FRM RAM and the 01h index

value will update the 32 MSB’s of row “0” FRM RAM.

To update the entire RAM location, the index is programmed only once with the starting value, “00”.

This is used inside the CS9211 to auto increment the FRM RAM locations for every FRM RAM data

access using the Offset 41Ch.

Offset 41Ch-41Fh

FRM Memory Data Register

Reset Value = 00000000h

31:0

FRM_DATA

FRM Memory Data Register: This 32-bit data represents FRM RAM data to be read or written to the

FRM RAM table in accordance to the RGB_SEL (Offset 418h[9:8]) and the index value (Offset

418h[5:0]).

Offset 420h-423h

Memory Control Register

Reset Value = 1EF80008h

31:5

RSVD

Reserved: These bits are not defined.

EDO_LATE

EDO DRAM Late Latch Bit: When this bit is set, the data is latched into the CS9211, one clock after

the data arrives from the DRAM. Since SSTN and TFT panels do not use any frame buffer, this bit is

used only for DSTN panels. This bit is effective only if EDO RAM is used, as selected by bit 0 = 0.

0 = Latch the data with no delay.

1 = Latch the data with a delay of one clock.

3EDO_EDGE_SEL

EDO Data Latch Edge Select: This bit controls which clock edge is used to latch data. When this bit

is set, the data from the DRAM is latched into the CS9211 on the negative edge of the memory clock.

Since SSTN and TFT panels do not use any frame buffer, this bit is used only for DSTN panels. This

bit is effective only if EDO RAM is used, as selected by bit 0 = 0.

0 = Latch on positive (rising) edge.

1 = Latch on negative (falling) edge.

SDRAM_LD

SDRAM Load Bit: SDRAM Load Mode Register. When enabled, this bit activates RAM refresh. Since

SSTN and TFT panels do not use any frame buffer, this bit is used only for DSTN panels.

0 = Disable; 1 = Enable.

Table 4-2. Configuration Registers (Continued)

Bit

Name

Description

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