CS9211 datasheet(46/62 Pages) NSC

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Revision 2.1

SDRAM_CLK

_INVERT

SDRAM Clock: Inverts the clock to the SDRAM interface. Since SSTN and TFT panels do not use

any frame buffer, this bit is used only for DSTN panels.

0= Useinverted clock.

1 = Use non-inverted clock.

SDRAM_EDO

SDRAM or EDO: Selects external frame buffer memory type. Since SSTN and TFT panels do not use

any frame buffer, this bit is used only for DSTN panels. 0 = EDO; 1 = SDRAM.

Offset 424h-427h

Dither RAM Control and Address Register

Reset Value = 00000000h

31:8

RSVD

Reserved: Set to 0.

DITHER_

RAM_ACCESS

Dither RAM Access Bit: Allows reads and writes to and from dither RAM.

0 = Disable (Do not allow reads or writes).

1 = Enable (Allow reads and writes).

To perform dither RAM reads and writes, bits 7 and 6 must be set to 1. In addition, Offset 40Ch bits 12

and 0 must be set to 1. If any of these bits are not set to 1, the RAM goes into power-down mode.

DITHER_

RAM_UPDT

Dither RAM Update: This bit works in conjunction with bit 7. If this bit is enabled, it allows the data to

update the RAM.

0 = Disable (do not allow dither RAM access).

1 = Enable (allow dither RAM access).

To perform dither RAM reads and writes, bits 7 and 6 must be set to 1. In addition, Offset 40Ch bits 12

and 0 must be set to 1. If any of these bits are not set to 1, the RAM goes into power-down mode.

5:0

DITHER_

RAM_ADDR

Dither RAM Address: This 6-bit field specifies the address to be used for the next access to the

dither RAM. Each access to the data register automatically increments the RAM address register. If

non-sequential access is made to the dither RAM, the address register must be reloaded before each

non-sequential data block.

Offset 428h-42Bh

Dither RAM Data Register (R/W)

Reset Value = 00000000h

31:0

DITHER_RAM_

DATA

RAM Data: This 32-bit field contains the read or write data for the RAM access.

Offset 42Ch-42Fh

Panel CRC Signature Register (R/W)

Reset Value = xxxxxxxxh

31:8

SIG_DATA

Signature Address (Read Only): 24-bit signature data for dither logic or FRM logic.

7:2

FRAME_CNT

Frame Count: Represents the frame count, which is an index for the generated signature for that

frame.

1SGFR

Signature Free Run: The value of this bit during the first cycle of a frame determines whether a sig-

nature will be generated for that frame. If this bit is kept high, with signature enabled (bit 0 = 1), the

signature generator captures data continuously across multiple frames. Changing this bit from high-to-

low causes the signature generation process to stop after the current frame.

0 = Do not capture signature during next frame.

1 = Capture signature during next frame.

SIG_EN

Signature Enable: Enables/disables signature capture. 0 = Disable; 1 = Enable.

Offset 430h-433h

Device and Revision ID Register (RO)

Reset Value = 92110303h

31:16

DEV_ID

Device ID (Read Only): This 16-bit field contains the data that represents the device ID.

15:0

REV_ID

Revision ID (Read Only): This 16-bit field contains the data that represents the revision ID.

Offset 434h-437h

GPIO Data Register (R/W)

Reset Value = xxxxxx00h

31:16

RSVD

Reserved (Read Only)

GPIO7_STS

GPIO7 Pin State (Read Only): Reports the value of pin GPIO7 when it is configured as an input.

GPIO6_STS

GPIO6 Pin State (Read Only): Reports the value of pin GPIO6 when it is configured as an input.

GPIO5_STS

GPIO5 Pin State (Read Only): Reports the value of pin GPIO5 when it is configured as an input.

GPIO4_STS

GPIO4 Pin State (Read Only): Reports the value of pin GPIO4 when it is configured as an input.

GPIO3_STS

GPIO3 Pin State (Read Only): Reports the value of pin GPIO3 when it is configured as an input.

GPIO2_STS

GPIO2 Pin State (Read Only): Reports the value of pin GPIO2 when it is configured as an input.

GPIO1_STS

GPIO1 Pin State (Read Only): Reports the value of pin GPIO1 when it is configured as an input.

GPIO0_STS

GPIO0 Pin State (Read Only): Reports the value of pin GPIO0 when it is configured as an input.

GPIO7_DATA

GPIO7 Pin Configuration: Reflects the level of GPIO7. 0 = Low, 1 = High. (Note)

GPIO6_DATA

GPIO6 Pin Configuration: Reflects the level of GPIO6. 0 = Low, 1 = High. (Note)

Table 4-2. Configuration Registers (Continued)

Bit

Name

Description

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