CS9211 datasheet(41/62 Pages) NSC

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Table 4-2. Configuration Registers

Bit

Name

Description

Offset 400h-403h

Panel Timing Register 1 (R/W)

Reset Value = 0000000h

RSVD

Reserved: This bit is not defined.

FP_VSYNC_POL

FP_VSYNC Input Polarity: Selects positive or negative polarity of the FP_VSYNC input signal (pin

99). Program this bit to match the polarity of the incoming FP_VSYNC signal. Note that Offset

404h[23] independently controls the polarity of the VSYNC output signal (pin 33).

0 = FP_VSYNC is normally low, transitioning high during sync interval (Default).

1 = FP_VSYNC is normally high, transitioning low during sync interval.

FP_HSYNC_POL

FP_HSYNC Input Polarity: Selects positive or negative polarity of the FP_HSYNC input (pin 97). Pro-

gram this bit to match the polarity of the incoming FP_HSYNC signal. Note that Offset 404h[22] inde-

pendently controls the polarity of the HSYNC output signal (pin 31).

0 = FP_HSYNC is normally low, transitioning high during sync interval (Default).

1 = FP_HSYNC is normally high, transitioning low during sync interval.

RSVD

Reserved: This bit is not defined.

HSYNC_SRC

TFT Horizontal Sync Source: Selects an internally generated or external pass-through source of the

TFT horizontal sync output on pin 31. The internally generated HSYNC pulse will be triggered by the

input HSYNC, but the output polarity, and leading and trailing edge positions are controlled by regis-

ters 404h[22] and 400h[7:0] respectively. The external mode will pass the input HSYNC pulse directly

to the output pin.

0 = Pass the input HSYNC directly onto the output LP/HSYNC pin (pin 31) (Default).

1 = Internally generate the output HSYNC using the leading/trailing edge bits [7:0] and the polarity bit

(Offset 404h[22]).

26:16

PAN_VSIZE

Panel Vertical Size: This field represents the panel vertical size in terms of scan lines. The value pro-

grammed should be equal to the panel size that is being connected.

This can be used only for DSTN/STN modes.

Example: 640x480 = 1E0h, 800x600 = 258h, and 1024x768 = 300h.

15:8

RSVD

Reserved: These bits are not defined.

7:5

HSYNC_LEADING

_EDGE

Horizontal Sync Leading Edge Position: Selects the position of the leading edge of the output

HSYNC pulse with respect to the rising edge of the modified input HSYNC pulse. The modified input

HSYNC pulse is that which has been inverted, or not inverted, by bit 29. The position is programmable

in steps of 1 DOTCLK, starting at 2 DOTCLOCKS and extending up to 8. Bit 27 must be set in order

for bits [7:5] to be recognized. Note that there are combinations of bits [7:5] and [4:0] that can result in

a zero- or negative-length pulse, for example if the trailing edge is positioned before the leading edge.

In this case, the output pulse will not be generated.

000 = No delay from the input HSYNC (Default).

001-111 = Position the HSYNC leading edge by 2 to 8 DOTCLKs with respect to the input HSYNC ris-

ing edge. Note that there is no setting for a position of 1 DOTCLOCK.

4:0

HSYNC_TRAILING

_EDGE

Horizontal Sync Trailing Edge Position: Selects the position of the trailing edge of the output

HSYNC pulse with respect to the rising edge of the modified input HSYNC pulse. The modified input

HSYNC pulse is that which has been inverted, or not inverted, by bit 29. The position is programmable

in steps of 1 DOTCLK, starting at 1 DOTCLOCK and extending up to 31. Bit 27 must be set in order

for bits [4:0] to be recognized. Note that there are combinations of bits [7:5] and [4:0] that can result in

a zero- or negative-length pulse, for example if the trailing edge is positioned before the leading edge.

In this case, the output pulse will not be generated.

00000 = Does not generate the HSYNC pulse if bit 27 = 0. (Default).

00001 - 11111 = The HSYNC trailing edge position can be varied from 1 to 31 DOTCLKs with respect

to the input HYSNC rising edge.

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