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数据搜索系统，热门电子元器件搜索 |
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CS9211 数据表(PDF) 40 Page - National Semiconductor (TI) |
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CS9211 数据表(HTML) 40 Page - National Semiconductor (TI) |
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40 / 62 page  www.national.com 40 Revision 2.1 4.0 Register Descriptions Table 4-1 provides a summary of the Configuration Regis- ters, followed by descriptions of the individual registers and their bit formats. These registers are accessed using the serial interface, as described in Section 3.2.1 “Serial Inter- face” on page 17. Note that all configuration registers are memory mapped. Table 4-1. Configuration Registers Summary Offset Access Name / Function Reset Value Reference (Table 4-2) 400h-403h R/W Panel Timing Register 1 Configures the flat panel horizontal and vertical timing characteristics 00000000h Page 41 404h-407h R/W Panel Timing Register 2 Configures the flat panel horizontal and vertical timing characteristics 00000000h Page 41 408h-40Bh R/W Power Management Register Configures the power management features of the LCD controller 00000000h Page 43 40Ch-40Fh R/W Dither and Frame Rate Control Register Configures dithering and frame rates 00000000h Page 44 410h-413h R/W Blue LFSR Seed 15-bit value that specifies the seed value for the FRM conversion of the Blue component of each pixel 00000000h Page 45 414h-417h R/W Green LFSR Seed 15-bit value that specifies the seed value for the FRM conversion of the Green component of each pixel Red LFSR Seed 15-bit value that specifies the seed value for the FRM conversion of the Red component of each pixel 00000000h Page 45 418h-41Bh R/W FRM Memory Index Register 00000000h Page 45 41Ch-41Fh R/W FRM Memory Data Register (32 x 64 Bits) 00000000h Page 45 420h-423h R/W Memory Control Register Selects the memory type, SDRAM or EDO DRAM 1EF80008h Page 45 424h-427h R/W Dither RAM Control and Address Register Provides the dither RAM address. The value programmed is used to initialize the Dither RAM address counter. Subsequent accesses to the Dither RAM Data Register cause the address counter to increment. 00000000h Page 46 428h-42Bh R/W Dither RAM Data Register Provides the Dither RAM data. The data can be read or written to the dither RAM via this register. Prior to accessing the data register, an appropriate address should be loaded to the Dither RAM Address Register (Offset 424h). Subsequent accesses to the data register cause the internal address counter to increment for the next cycle. 00000000h Page 46 42Ch-42Fh R/W Panel CRC (Cyclical Redundancy Check) Signature Register When CRC is enabled, the CRC logic writes the generated signature to this register. The value can be compared with the software simulation results or a previously generated signature for the same image and settings. xxxxxxxxh Page 46 430h-433h RO Device and Revision ID Register Reads the CS9211’s device ID and revision ID. 92110302h Page 46 434h-437h R/W GPIO Data Register Status and levels of GPIO pins. xxxxxxxxh Page 46 438h-43Bh R/W GPIO Control Register Configuration of each GPIO pin as an input or output, and in normal or weak pull-up/down modes. xxxxxxxxh Page 47 |
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