CS9211 datasheet(10/62 Pages) NSC

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Revision 2.1

Signal Definitions (Continued)

2.2.2

Serial Interface Signals

Signal Name

Pin No.

Type

(Drive)

Description

SCLK

Serial Interface Clock

This input signal is the clock for the serial control interface. Data is clocked in

and out on the rising edge. The other serial interface signals (SDIN, SCS,

and SDO) are synchronous to this signal.

SDIN

Serial Data Input

This is the data input line for the serial control interface. Input data is serial-

ized on this pin, including the command stream for register reads and writes.

SDO

(8 mA)

Serial Data Output

This is the data output line for the serial control interface. Output data is seri-

alized on this pin in response to register read commands.

SCS

Serial Chip Select

This active high chip select indicates when valid data is being clocked in or

out via the SDIN/SDO pins.

2.2.3

Flat Panel Interface Signals

Signal Name

Pin No.

Type

(Drive)

Function

Selection

Description

SHFCLK

(12

mA)

---

Panel Clock (Shift Clock)

This is the shift clock or pixel clock for the flat panel data.

This signal is used to clock pixel data into the LCD panel.

Depending on the type of panel being interfaced, this signal

can alsobereferred toasCL2 or SHIFT.

UD[11:0]

LD[11:0]

3:14

15, 16,

20:29

(8 mA)

---

Upper and Lower Scan Data

These outputs are the panel pixel data bus to the LCD

panel. The data format is dependent on the panel type

selected. Refer to Section 3.2.2 “Mode Selection” on page

19.

LDE

(8 mA)

Offset

404h[25] = 1

Flat Panel Display Enable (TFT Panels)

LDE is the display enable for active-matrix TFT panels and

is used to indicate the active pixel data on UD[11:0] and

LD[11:0].

(8 mA)

Offset

404h[26] = 0

Latch Pulse (SSTN/DSTN Panels)

Latch Pulse is the line pulse or latch pulse for the flat panel

data, indicating that a display line is about to start.

Depending on the type of panel being interfaced, this signal

can alsobereferred toasCL1 or LINE.

HSYNC

Offset

404h[26] = 1

Horizontal Sync (TFT Panels)

HSYNC is the horizontal sync for the active-matrix TFT

panel. This is a delayed version of the input HSYNC signal

with the appropriate pipeline delay relative to the pixel data

on UD[11:0] and LD[11:0].

If pin 31 is set as HSYNC at Offset 404h[26], its polarity is

programmable through Offset 404h[22]:

0= Active high; 1 = Active low.

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