CS9211 datasheet(17/62 Pages) NSC

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Revision 2.1

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Functional Description (Continued)

3.2.1

Serial Interface

Two commands are defined for the serial interface, a read

command and a write command. The read and write proto-

cols are summarized in Table 3-1. Figure 3-5 on page 18

shows the write cycle timing, and Figure 3-6 on page 18

shows the read cycle timing. In order for the CS9211 to

properly receive commands through the serial interface,

the DOTCLK input signal must be active.

The protocol begins with the assertion of the SCS input,

followed by activity on the SCLK (serial command clock)

and SDIN (serial data input) lines. The serial data must be

in the following order: one start bit (value = X), one control

bit (value = 1), 12 address bits, a read/write command bit

(1 =Write, 0 =Read), and32data bits. In thecaseofa

read, seven (7) idle clock pulses must occur between the

read command and the beginning of the 32 bits of data

transmission on the SDO line. After the last bit of the serial

data transfer, SCS should be deasserted.

The CS9211 samples the serial interface input signals on

the rising edge of SCLK. Therefore, data driven onto the

SDIN input should change on the falling edge of SCLK.

Data driven by the CS9211 onto the SDO output changes

on the rising edge of SCLK. Therefore data being read

should be sampled on the falling edge of SCLK.

3.2.1.1

Write Transfer Sequence (52 clocks)

Assert SCS input.

One SCLK period “don’t care” transfer (i.e., clock tog-

gle).

Write a 1 to SDIN.

Next, the address is transmitted with the LSB

(Address[0]) first... MSB (Address[11]) last.

The Write bit = 1.

The data is transmitted LSB (Data[0]) first... MSB

(Data[31]) last, on the positive edges of the next 32

SCLKS.

Deassert SCS (one clock period) and toggle SCLK for

four clock periods.

3.2.1.2

Read Transfer Sequence (56 clocks)

Assert SCS input.

One SCLK period “don’t care” transfer (i.e., clock tog-

gle).

Write a 1 to SDIN.

Next the address is transmitted with the LSB

(Address[0]) first ... MSB (Address[11]) last.

TheReadbit =0.

Seven SCLK periods of “don’t care” transfer (i.e., clock

toggles).

The dataistransmittedonSDO with theLSB (Data[0])

first ... MSB (Data[31]) last, on the positive edges of

the next 32 SCLK .

Deassert SCS (one clock period) and toggle SCLK for

one clock period.

Table 3-1. Serial Interface Write/Read Sequences

Cycle(s)

Write Sequence with SCS = “1”

Cycle(s)

Read Sequence with SCS = “1”

1 Start bit

SDIN = Don’t care

1 Start bit

SDIN = Don’t care

1 Control bit

SDIN = 1

1 Control bit

SDIN = 1

12 Address bits

SDIN = 4xx

12 Address bits

SDIN = 4xx

1 Write bit

SDIN = 1

1 Read bit

SDIN = 0

32 data bits

ex: SDIN = A8A8_A8A8h

7 Idle SCLKs

ex: SDIN = Don’t care

32 Read data bits

ex: SDO = A8A8_A8A8h

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