CS9211 datasheet(12/62 Pages) NSC

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Revision 2.1

Signal Definitions (Continued)

DQMH

121

(8 mA)

Data Input/Output Mask

DQMx is an input mask signal to the frame buffer SDRAM for write accesses

and an output enable signal for read accesses.

• Input data to the SDRAM is masked when DQMx is sampled high during

a write cycle.

• The output buffers are placed in a High-Z state (two-clock latency) when

DQMx is sampled high during a read cycle.

DQMH corresponds to DQ8-DQ15 of the SDRAM.

DQML corresponds to DQ0-DQ7 of the SDRAM.

This signal is not used for EDO DRAM.

DQML

120

(8 mA)

OE#/BA

133

(8 mA)

Output Enable and Bank Select Address

This pin is the output enable for the DRAM and the bank address selection

for SDRAM.

BA defines to which bank the active, read, write or precharge command is

being applied. This function is not used in the CS9211.

RAS#

130

(8 mA)

Row Address Strobe

The row address strobe for DRAM/SDRAM.

CASH#

124

(8 mA)

Column Address Strobe

The column address strobe for the upper byte of EDO DRAM. This pin

should not be connected if SDRAM is used.

CAS#/CASL#

127

(8 mA)

Column Address Strobe

The column address strobe for the lower byte of DRAM. This pin should be

connected (to CAS#) if SDRAM is used.

WE#

122

(8 mA)

Write Enable

The write enable output for DRAM/SDRAM.

MCLK

123

(12

mA)

Memory Clock

This clock output from the CS9211 should be connected to the SDRAM. It is

not used for EDO DRAM.

CKE

129

(8 mA)

Clock Enable

This output signal should be connected to the SDRAM. When CKE is active

(high), the MCLK signal is low. Deactivating the clock provides precharge

power-down and self-refresh operations (all banks idle), active power-down

(row active CKE in either bank) or clock Suspend operation (burst/access in

progress).

CKE is synchronous to MCLK, except after the device enters power-down

and self refresh modes, where CKE becomes asynchronous until after exit-

ing the same mode. The input buffers, including MCLK, are disabled during

power-down and self refresh modes, and provide low power. CKE may be

tied high.

This signal is not used for EDO DRAM.

CS#

131

(8 mA)

Chip Select

This output is connected to the chip select of SDRAM. CS# enables (regis-

tered low) and disables (registered high) the command decoder of the

SDRAM. All commands are masked when CS# is deasserted (high).

2.2.4

Memory Interface Signals (Continued)

Signal Name

Pin No.

Type

(Drive)

Description

CS9211 数据表(PDF) 12 Page - National Semiconductor (TI)

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CS9211 数据表(PDF) 12 Page - National Semiconductor (TI)

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