CS9211 datasheet(28/62 Pages) NSC

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Revision 2.1

Functional Description (Continued)

3.2.4.1

Removal of Flickering

One side effect of frame rate modulation is flickering. If a

large group of pixels on an LCD panel were the exact same

intensity, and all of the pixels in this large group were blink-

ing on and off together in synchronization, the flickering

effect would be detectable by the human eye. The CS9211

removes detectable flickering by de-synchronizing adjacent

pixels so that they do not blink on and off at the same time.

The de-synchronization is implemented by using two linear

feedback shift registers (LFSR) to randomize the switching

sequences of each individual pixel on the display. A 15-bit

LFSR, which is advanced every pixel clock, is used to gen-

erate global randomization. A 9-bit LFSR, which is

advanced every HSYNC, is used to generate local random-

ization. Both LFSRs are reset every frame. The addition of

the lower 6 bits of these two LFSRs gives each pixel a

pseudo-randomized index into the chosen 64-bit word of

the corresponding FRM RAM Table. Using this index and

frame count, every pixel on the display starts the switching

sequence from 1 of the 64 possible positions pseudo-ran-

domly and completes one sequence in 64 frames.

In order to randomize the switching sequence further, each

primary color FRM RAM Table has an independent 15-bit

LFSR, with its own seed value. These seed values are fully

programmable. The only side effect of this implementation

is motion artifactsonthe display, whichiscommoninFRM

implementations. As long as the refresh rate of the LCD

panel is high, this effect should not be noticeable.

3.2.5

FRM Memory

The three 32 x 64 FRM memories are programmed through

the serial interface. There is one separate FRM look-up

table for each primary color (R, G, and B). Table 3-11

shows the registers used to program the FRM RAM tables.

The FRM RAM tables can be programmed either individu-

ally or all together using the register Offset 418h[9:8]. Reg-

ister Offset 418h[5:0] is used to select the initial FRM RAM

index, which automatically increment with each read or

write operation. Register Offset 41Ch[31:0] is used to

access the actual FRM RAM data. Two 32-bit register

accesses are required to fill one 64-bit FRM RAM location.

Table 3-11. FRM Memory Access Control Bits

Bit

Name

Description

Offset 418h-41Bh

FRM Memory Index Register (R/W)

Reset Value = 00000000h

9:8

RGB_SEL

RGB Memory (FRM RAM) Select: Allows reading or writing to individual R,G, and B memory FRM

RAM locations or writing to all of them at the same time.

00 = Read from R FRM RAM but write to RGB FRM RAM.

01 = read or write to R FRM RAM.

10 = Read or write to G FRM RAM.

11 = Read or write to B FRM RAM.

Note: All FRM RAMs can be accessed through the serial interface before the panel is powered up.

5:0

FRM_INDEX

FRM Memory Index: This auto-incrementing value represents the index to the FRM RAM. Each RAM

is configured as 32x64, requiring two index values to update each row of FRM RAM.

For example, the 00h index value will update the 32 LSB’s of row “0” FRM RAM and the 01h index value

will update the 32 MSB’s of row “0” FRM RAM.

To update the entire RAM location, the index is programmed only once with the starting value, “00”.

This is used inside the CS9211 to auto increment the FRM RAM locations for every FRM RAM data

access using the Offset 41Ch.

Offset 41Ch-41Fh

FRM Memory Data Register

Reset Value = 00000000h

31:0

FRM_DATA

FRM Memory Data Register: This 32-bit data represents FRM RAM data to be read or written to the

FRM RAM table in accordance to the RGB_SEL (Offset 418h[9:8]) and the index value (Offset

418h[5:0]).

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