THS8083APZP datasheet(42/64 Pages) TI

42 / 64 page

4–2

4.2

Timing Diagram—16-Bit Parallel Mode

This is the ITU–R.BT–601 style mode typically used in YUV operation of the part with a Y analog input connected

to the Ch1 input of the THS8083A, and with Cb and Cr connected to the Ch2 and Ch3 inputs, respectively. The

DATACLK1 output is at the sampling clock frequency and Ch3 remains unused. The output bus B of all channels is

high impedance. The HS_D signal can be used to uniquely identify output data Cb from Cr.

DATACLK

CH1_OUTA[7..0]

CH2_OUTA[7..0]

CH2_OUTB[7..0]

CH1_OUTB[7..0]

CH3_OUTA[7..0]

CH3_OUTB[7..0]

DHS

Cb: From Ch.2 Input

Cr: From Ch.3 Input

pix 01

pix 02

ADCCLK2

tPLH(OE)

tPHL(OE)

tsu(OUT)

th(OUT)

th(DHS)

tsu(DHS)

<DHS_MODE> = 1 –> Width

Equal to Width of HS Input

<DHS_MODE> = 0 –> DHS

Width is 1 ADCCLK2 Period

7 ADCCLK2

Cycles Latency

(DHS_POL = 0

Assumed-Inverted

Polarity Otherwise)

7 ADCCLK2 Cycles Latency

Last Samples From Previous Line

01(Cr)

01(Cb)

03(Cb)

Last Samples From Previous Line

THS8083APZP 数据表(PDF) 42 Page - Texas Instruments

THS8083APZP 数据表(HTML) 42 Page - Texas Instruments

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