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THS8083APZP 数据表(PDF) 12 Page - Texas Instruments |
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THS8083APZP 数据表(HTML) 12 Page - Texas Instruments |
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12 / 64 page  1–6 1.7 THS8083A Terminal Functions Order (Continued) TERMINAL I/O/B† TYPE‡ DESCRIPTION NAME NO. I/O/B† TYPE‡ DESCRIPTION CLOCK I/O XTL1_MCLK 20 I A Master crystal connection 1 (connects 14.318-MHz crystal) or master clock input (at 14.318 MHz) XTL2 22 O A Master crystal connection 2 (connects 14.318-MHz crystal) DATACLK1 54 O D 1st clock output: DATACLK1 The rising edge of this clock can be used by an external device to clock in THS8083A output data in all modes (see output timing diagrams in Section 4 for more details). ADCCLK2 53 O D 2nd clock output: ADCCLK This clock output is equal to the clock of the ADC converter, optionally inverted and/or divided-by-2. DTOCLK3 52 O D 3rd clock output: DTOCLK. This clock output is the output of the DTO. EXT_ADCCLK 56 I D External clock input for A/D channels, at pixel clock frequency ANALOG SIGNAL I/O CH1_IN 81 I A Analog input channel 1. Since this channel includes the composite sync slicer and is not downsampled in 4:2:2 mode, this channel should be used for green or luminance input, if any of these features are used. CH2_IN 88 I A Analog input channel 2. In YUV 4:2:2 sampling mode, Pb should be connected to this input to generate a ITU.BT-601 style output. CH3_IN 95 I A Analog input channel 3. In YUV 4:2:2 sampling mode, Pr should be connected to this input to generate a ITU.BT-601 style output. VREFBO_CH1 82 B A Reference voltage bottom output channel 1. In normal operation: output. For a specific configuration, this terminal becomes an input terminal (see Powerdown section in Functional Description). VREFTO_CH1 83 B A Reference voltage top output channel 1. In normal operation it is an output. For a specific configuration, this terminal becomes an input terminal (see Powerdown section in Functional Description). VREFBO_CH2 89 B A Reference voltage bottom output channel 2. See VREFBO_CH1. VREFTO_CH2 90 B A Reference voltage top output channel 2. See VREFTO_CH1. VREFBO_CH3 96 B A Reference voltage bottom output channel 3. See VREFBO_CH1. VREFTO_CH3 97 B A Reference voltage top output channel 3. See VREFTO_CH1. VMID 73 B A Midlevel input range (input common mode). In normal operation it is an output. For a specific configuration, this terminal becomes an input terminal (see Powerdown section in Functional Description). VCM 72 O A Common mode voltage output (approximately 1.5 V) DIGITAL SIGNAL I/O CH1A0 42 O D Display output channel 1, bus A, bit 0 (LSB) CH1A1 43 O D Display output channel 1, bus A, bit 1 CH1A2 44 O D Display output channel 1, bus A, bit 2 CH1A3 45 O D Display output channel 1, bus A, bit 3 CH1A4 46 O D Display output channel 1, bus A, bit 4 CH1A5 47 O D Display output channel 1, bus A, bit 5 CH1A6 48 O D Display output channel 1, bus A, bit 6 CH1A7 49 O D Display output channel 1, bus A, bit 7 (MSB) CH1B0 63 O D Display output channel 1, bus B, bit 0 (LSB) CH1B1 64 O D Display output channel 1, bus B, bit 1 † I = input to device: O = output from device B = bidirectional ‡ A = analog pin: D = digital pin |
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