THS8083APZP datasheet(18/64 Pages) TI

18 / 64 page

2–4

2.3.1

Implementation When Using Channel 1 Sync Slicing From Ch1 as Selected by CS_SEL,

or on Prerevision A Silicon

To support sync-on-Y/sync-on-G extraction, users should provide an external dc biasing to the Y/G channel. This can

be done by establishing a dc clamp through a diode with its cathode connected to the ac-coupling capacitor (at the

side of the THS8083A) on the AGY channel and its anode connected to a dc level. Since the slicing level is

approximately 1.35 V and the sync amplitude is –300 mV, the negative sync-tip should be clamped by the diode to

a level of approximately 1.2 V. For example, using a Schottky switching diode (type 1N5711) with a maximum low

forward voltage drop of 0.4 V, the dc level at the anode can be approximately 1.6 V. This level can be derived through

a resistive voltage divider off the power supply.

2.4

Programmable Gain Amplifier (PGA)

Each video channel is passed through a programmable gain amplifier, to provide a full-scale signal to each A/D. The

user can change this gain via register programming. A gain change becomes effective immediately.

The range of the PGA is such that an input ac range from 0.4 Vpp to 1.2 Vpp can be scaled to ADC full scale, by

maximum gain and minimum gain settings respectively.

The PGA is split into a 6-bit coarse gain control and 5-bit fine gain control. Their combination leads to a PGA resolution

of better than 1 LSB on the ADC output code.

The bandwidth of the PGA is by design constant, resulting in a constant analog video input bandwidth.

The coarse PGA, with its 64 settings, covers a 4/3 x to 4x gain change, used for a 0.4 V (0.4 Vpp

× 4 = 1.6 Vpp)

respectively 1.2 Vpp (1.2 Vpp

× 4/3 = 1.6 Vpp) input range swing.

While an amplifier with variable gain implements the coarse PGA, the fine PGA is implemented by slightly changing

the top and bottom reference levels that are also independently controllable for each ADC channel. The fine range,

with its 32 settings, covers a range of 16 LSBs.

The fine and coarse PGA settings can be combined into a single PGA gain formula as follows:

GAIN = (4/3 + C/24)(1 + (F–15)/512)

Where C is the coarse gain setting (0..63) and F the fine gain setting (0..31).

2.5

A/D Converter

The A/D converter’s switched-capacitor single-pipeline CMOS architecture combines excellent signal-to-noise

characteristics with a very wide 3-dB analog input bandwidth of typically 500 MHz. The A/D block contains an internal

reference voltage generator, providing stable bottom and top references derived from an internal bandgap reference.

The reference voltages are made available externally. The THS8083A supports both dc and ac-coupled inputs

(clamping disabled). With dc-coupling, available external references can be used to level-shift the input signal.

The A/D converter is assured up to 80 MSPS with no missing codes. The sampling clock of the A/D converter is either

externally fed or internally generated by the PLL.

2.6

PLL

The PLL is a fully contained functional block consisting of:

•

An analog PLL operating at a fixed output frequency of N times the master (crystal) clock frequency

•

A digital PLL containing a digital phase-frequency detector (PFD), a discrete time oscillator (DTO), a digital

loop filter, a feedback divider, a programmable clock output divider, and a programmable phase shifter

2.6.1

Analog PLL

The analog PLL generates a high-frequency internal clock used by the DTO in the digital PLL to derive the pixel output

frequency with programmable phase. The reference signal for this PLL is the master clock frequency supplied on the

XTL1-MCLK terminal.

THS8083APZP 数据表(PDF) 18 Page - Texas Instruments

THS8083APZP 数据表(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

数据表下载