THS8083APZP datasheet(19/64 Pages) TI

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2–5

Two options exist for connecting a master clock:

•

A crystal can be connected between the XTL1-MCLK and XTL2 terminals. The device provides internal

oscillator circuitry.

•

A 3.3-V CMOS/TTL clock signal can be connected to XTL1-MCLK from an external oscillator. In this case

XTL2 must be left unconnected.

The port is designed to operate from a master clock frequency of 14.31818 MHz, which is a standard frequency in

video applications: 4x is the subcarrier frequency for NTSC. Many low-cost crystals are available for this frequency.

The default internal oscillator operates at 8x the master clock frequency, or about 114 MHz. This setting of 8x, which

is the value of the feedback divider in the analog PLL loop, is programmable (VCODIV register value). Normally this

remains as the default 8x value. Users can change this value when a master clock of a different frequency is

connected. In this case care should be taken to keep the internal high-frequency clock (i.e., master clock frequency

x analog feedback divider) lower than 120 MHz. The higher this internal frequency, the better the frequency resolution

of the DTO.

When a crystal is used as the master clock source, it is not advised to use another frequency than the recommended

14.31818 MHz, since the internal oscillator circuitry is not production tested at other frequencies. If another master

clock is used, it is recommended to drive XTL1–MCLK by a direct clock signal. VCODIV should be programmed such

that the internal clock remains close to but less than 120 MHz.

14.31818 MHz

Phase-

Frequency

Detector

Loop

Filter

VCO

Programmable

Divider

VCODIV

VCOCLK

(To Digital PLL)

Figure 2–5. Analog PLL

2.6.2

Digital PLL

The digital PLL loop derives the ADC (pixel) clock frequency from the high-speed internal clock. A DTO generates

an output frequency from a user-programmable DTO increment. To operate over the 13–80 MHz range, an extra DTO

clock output divider can be switched in. Appendix A shows the formula that relates the frequency of the internal

high-speed clock, the DTO increment value, and the DTO clock output divider to the PLL output frequency.

The PLL output, after the clock divider, is sent to the programmable feedback divider (TERM_CNT register value).

This value is typically programmed with the number of total pixels per line for a given video/graphics format. The

output of this divider is then one input to the phase-frequency detector. Its other input is typically the horizontal sync

(HS) reference of a graphics/video signal. HS needs to be provided as a separate TTL/CMOS type signal to the

dedicated input terminal. See the Composite Sync Slicer section to use the PLL in the case of input signals with a

composite sync. The polarity of HS is programmable (HS_POL register value).

Both HS and VS inputs on the THS8083A can accept a 3-V and a 5-V logic-compliant signal.

On the HS input, as on the VS input, a digital noise gate can be optionally switched in (HS_MS and VS_MS register

values, respectively). The user can program the minimum number of clock cycles that have to be present in HS and

VS before they are interpreted as a valid HS and VS. This avoids having any spikes being interpreted as an active

HS and falsely updating the PLL.

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