THS8083APZP datasheet(44/64 Pages) TI

部件名	THS8083APZP

功能描述	TRIPLE 8 BIT 80 MSPS 3.3V VIDEO AND GRAPHICS

PDF	64 Pages

Scroll/Zoom	100%

制造商	TI [Texas Instruments]

网页	http://www.ti.com

标志

44 / 64 page

4–4

4.4

Timing Diagram—48-Bit Parallel Mode

This mode allows a double-pixel width output interface with no time offset between buses A and B. The DATACLK1

output is at half of the sampling clock frequency. Data on output bus A precedes data on output bus B.

Last Samples From Previous Line

DATACLK

CH1_OUTA[7..0]

CH2_OUTA[7..0]

CH2_OUTB[7..0]

CH1_OUTB[7..0]

CH3_OUTA[7..0]

CH3_OUTB[7..0]

DHS

tdlh(OE)

tdhl(OE)

tsu(DHS)

th(DHS)

tsu(OUT)

(DHS_POL = 0

Assumed-Inverted

Polarity Otherwise)

<DHS_MODE> = 1 –> Width

Equal to Width of HS Input

<DHS_MODE> = 0 –> DHS

Width is 1 ADCCLK2 Period

7 ADCCLK2

Cycles Latency

pix 01

pix 02

ADCCLK1

Last Samples From Previous Line

th(OUT)

Last Samples From Previous Line

7 ADCCLK2 Cycles Latency

THS8083APZP 数据表(PDF) 44 Page - Texas Instruments

THS8083APZP 数据表(HTML) 44 Page - Texas Instruments

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THS8083APZP 数据表(PDF) 44 Page - Texas Instruments

THS8083APZP 数据表(HTML) 44 Page - Texas Instruments

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