THS8083APZP datasheet(43/64 Pages) TI

43 / 64 page

4–3

4.3

Timing Diagram—48-Bit Interleaved Mode

This mode allows a double-pixel width output interface with one sampling clock period time offset between buses A

and B. The DATACLK1 output is at half of the sampling clock frequency. Data on output bus A precedes data on output

bus B.

DATACLK

CH1_OUTA[7..0]

CH2_OUTA[7..0]

CH2_OUTB[7..0]

CH1_OUTB[7..0]

CH3_OUTA[7..0]

CH3_OUTB[7..0]

pix 01

pix 02

ADCCLK2

DHS

tPLH(OE)

tPHL(OE)

tsu(DHS)

th(DHS)

tsu(OUT)

th(OUT)

tsu(OUT)

th(OUT)

(DHS_POL = 0

Assumed-Inverted

Polarity Otherwise)

7 ADCCLK2 Cycles Latency

Last Samples From Previous Line

<DHS_MODE> = 1 –> Width

Equal to Width of HS Input

<DHS_MODE> = 0 –> DHS

Width is 1 ADCCLK2 Period

7 ADCCLK2

Cycles Latency

THS8083APZP 数据表(PDF) 43 Page - Texas Instruments

THS8083APZP 数据表(HTML) 43 Page - Texas Instruments

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