THS8083APZP datasheet(14/64 Pages) TI

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1.7

THS8083A Terminal Functions Order (Continued)

TERMINAL

I/O/B†

TYPE‡

DESCRIPTION

NAME

NO.

I/O/B†

TYPE‡

DESCRIPTION

DIGITAL CONTROL I/O

SCL

Clock for I2C. Although the device is an I2C slave, this signal can be held low by the device

to signal contention, therefore it is flagged bidirectional.

SDA

Serial data for I2C

I2CA

Address select for I2C

0 = LSB of device address 0

1 = LSB of device address 1

EXT_CLP

External clamp timing pulse. Positive polarity required.

Reference clock input for PLL (horizontal sync input). Polarity selectable via I2C register

<HS_POL>. 5-V tolerant input

Vertical sync input. Polarity selectable via I2C register <VS_POL>. 5 V tolerant input

DHS

Display horizontal sync. This output can be generated as either a delayed version of

input HS or as output pulse from the PLL feedback divider. See Display Horizontal

Sync section in Functional Description.

CS/TEST1

A/D

Composite sync output. This output produces a 3-V logic-compatible sliced output of

CH1 or CS_IN, depending on CS_SEL (see CS_IN/TEST2 terminal). When present

and enabled, CS carries the embedded composite sync. See Composite Sync Slicer

section in Functional Description. For TI internal testing, this pin can also be configured

as a test pin. Leave unconnected when CS output signal is not used.

CS_IN/TEST2

Composite sync slicing input. When selected by CS_SEL register, the signal on this pin

is clamped to blanking level according to the clamp timing pulse and sliced approxi-

mately 150 mV below this clamped level to produce a composite sync output available

on CS/TEST1. This pin can also be configured as a test pin for TI internal testing.

Leave unconnected when CS input signal is not used.

LOCK

100

Lock detect output

0 = unlocked

1 = locked

PFD_FREEZE

Freezes the PLL output frequency by stopping the PFD output (i.e., keeping last

increment to DTO). See section 2.3 Composite Sync Slicer.

0 = updating

1 = frozen

Output enable for data output busses A and B. Data outputs are active only when

OE = L and the corresponding bus is active for the current output formatter mode

(register OFM_CTRL). When data outputs are not active or when DVDD = 0 V, data

output is Hi-Z. The clock outputs are not affected by OE.

0 = enabled

1 = disabled

RESET

General chip reset (active low). The reset is a synchronous reset. Therefore, a master

clock on XTL1–MCLK needs to be present for proper reset.

TEST I/O

CS/TEST1

A/D

See previous description for this terminal under DIGITAL CONTROL I/O.

TEST2

A/D

See previous description for this terminal under DIGITAL CONTROL I/O.

SCAN_TEST

Input for scan-path activation:

0 = disabled

1 = enabled.

This pin MUST be tied low for normal operation and is of use for TI internal testing only.

UNUSED PINS

80, 86, 87,

93, 94

Not connected. Tie to a fixed high or low level on board.

† I = input to device: O = output from device B = bidirectional

‡ A = analog pin: D = digital pin

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